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wireless receiver architectures


Introduction
In wireless communication receivers, the received radio frequency (RF) signal should be downconverted to baseband and sampled for further processing in digital
domain. The received signal is processed first in the analog domain and passed on to the digital domain, and thus analog-to-digital and digital-to-analog conversions should occur somewhere in the receiver path. So, there are choices of receiver architectures according to where to put the analog-to-digital converter (ADC) and the digital-to analog converter (DAC) and how to downconvert the received signal. It ranges from the traditional heterodyne architecture to digital-IF architectures. In this chapter, some of the important receiver architectures such as heterodyne, direct conversion, low-IF, and digital-IF receiver architectures are briefly summarized.

2.2 Heterodyne Receiver Architecture
In the heterodyne receiver architecture shown in Figure an RF signal is downconverted to an intermediate frequency (IF) by the first mixer. Then the signal is I/Q separated and downconverted to baseband by the second mixers. The firstband pass filter (BPF) located in front of the low noise amplifier (LNA) is for frequency band selection. The second BPF is for image rejection, and the third BPF and a low pass filer (LPF) are for channel selection. After low pass filtering for channel selection, the signal is sampled at baseband, which is called baseband sampling. As shown in Figure, the channel selection is done at IF as well as at baseband before ADC, which relaxes the Q required of each channel selection filter. The heterodyne architecture has been the most popular receiver architecture for a long time due to its good selectivity and sensitivity and can be found in many commercial RF transceivers. It relaxes the dynamic range of the baseband circuits. But, normally the IF band pass filter and the image reject (IR) filter are external components, which makes this architecture not suitable for monolithic integration.

2.3 Direct Conversion Receiver Architecture
Fig. shows a direct conversion receiver (DCR) architecture which is also known as homodyne or zero-IF receiver architecture. In practice, an RF band selection filter is placed between an antenna and an LNA, but it is not shown in the figure for simplicity. The DCR downconverts the desired signal directly from RF to DC and utilizes the baseband sampling. Thus, the DCR eliminates the need for discrete image rejection (IR) as well as intermediate frequency (IF) filters, which makes it suitable for monolithic integration. In addition, as the desired signal band is downconverted to the baseband at the early stage in the receiver chain, it is relatively easy to design the baseband circuits for multistandard operation. That is, the channel selection and automatic gain control (AGC) in DCRs are done at baseband using on-chip low pass filters and variable gain amplifiers which can be made to work for multiple wireless communication standards with low cost and less current consumption. Since the information bearing signal and blockers are translated to baseband together and channel selection is done at baseband, the DCR usually requires high dynamic range baseband circuits. This architecture becomes the most popular architecture in implementing an integrated single-chip receivers, but the main problems are DC offset problem and I/Q mismatch.

2.4 Low-IF Receiver Architecture
As shown in Fig. 2.3, the low-IF architecture looks quite similar to the direct conversion architecture except that it downconverts the received signal not to DC but to a low intermediate frequency (IF). The low-IF architecture also does not need external IF and IR filters, which makes it suitable for monolithic implementation. In addition, it does not suffer from DC offset problem which is the main problem in DCRs. But it has an image problem, so it needs integrated poly-phase filter for image rejection.

2.5 Digital-IF Receiver Architecture
Fig. 2.4 shows the digital-IF architecture where an RF signal is downconverted to IF by an analog mixer and directly sampled at IF. Low frequency operation such as the second mixing and filtering are performed in digital domain, which is called IF sampling. Since the I and Q are not separated in the analog domain, only one ADC is necessary instead of two ADCs and I/Q mismatch problem is avoided. At least tne analog IF stages can be eliminated compared to heterodyne architecture. Since analog-to-digital conversion is done at IF, the baseband can be very easily made programmable. So, this architecture is suitable for multistandard operation. The main difficulty in this architecture is to achieve very high ADC requirements such as very low quantization and thermal noise, very high clocking rate, high linearity, wide dynamic range, wide input bandwidth. Heavy anti-aliasing filtering may be costly formobile units.





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