Very Large Scale Integration (VLSI) design plays a significant role in the fabrication of modern Integrated Circuits (ICs) with smaller in size and with more features for any electronics systems. Power consumption has become one of the biggest challenges in high1performance VLSI design. Designers are thus continuously challenged to come up with innovative ways to reduce power while trying to meet all the other constraints imposed on the design. As a consequence, a lot of low power design techniques have been proposed at all levels of the design hierarchy. However, all these techniques focus on low power dissipation. Advancements in semiconductor fabrication technology has helped the design engineers to accommodate more number of transistors in a VLSI chip. With the proliferation of mobile battery1powered devices, reduction of power in the embedded VLSI chips has become an active area of research. During the last decade, power reduction techniques have been proposed at all levels of the design hierarchy from system to device levels. For the development of complex, high performance, low power devices implemented in deep submicron technology, power management is a critical parameter and it cannot be ignored even during testing. With the increase in the density of the chips, the problem of testing has also increased manifold. A related problem is to achieve power reduction during the actual testing of a chip. Power consumption in test mode is considerably higher than the normal functional mode of a chip. The reason is that test patterns cause as many nodes switching as possible, while a power saving system mode only activates a few modules at a time. Thus, during testing switching activity in all the internal lines of a chip is often several times higher than during normal operation. Sometimes parallel testing is used in SoCs to reduce test application time, which results in excessive power dissipation. Again, successive functional input vectors applied to a given circuit during system mode have a significant correlation, while the correlation between consecutive test patterns can be very low. Usually, there is no definite correlation between the successive test patterns generated by an ATPG (for external testing) or by an LFSR (for BIST) for testing of a circuit. This can cause significantly RECENT ADVANCES in NETWORKING, VLSI and SIGNAL PROCESSING ISSN: 1790-5117 113 ISBN: 978-960-474-162-5larger switching activity in the circuit during testing than that during its normal operation. Low power dissipation during test application is becoming an equally important figure of merit in today’s VLSI circuits design with BIST and is expected to become one of the major objectives in the near future. In this paper we have proposed an AI1based approach to reorder the test vectors such that the switching activity and hence the power dissipation during testing is reduced.