vlsi project-Redundant low power 2T-2C DRAM
The most straightforward low-power technique is voltage down-scaling. However, if scaling down the supply voltage of a given circuit, it becomes slower and less reliable (more susceptible to noise). In a standard 1T-1C DRAM cell, the charge stored on the capacitor – which is representative of the stored data bit – decays over time due to leakage currents. This is why standard DRAMs need to be refreshed every 2 to 4ms. Now, when scaling down the supply voltage and deliberately choosing smaller capacitors, the maximum data retention time is even shorter, but still long enough for many applications such as LDPC/Turbo decoders. For a given application, we can deﬁne a minimum data retention time, which in turn implies a minimum capacitor size. However, when implementing a minimum C DRAM on a chip, it is possible that some data be lost, because of a remaining uncertainty in behaviour due to process variations. In order to detect 2a loss of data, redundancy can be added to each storage cell: both the data bit and its logic complement are stored within one cell, which now is a 2T-2C cell. Fig. 2 shows the schematic view of such a storage cell.