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VLSI project idea- Test chip for standard cell based memories


Memories to be integrated on a given chip can be built from standard cells. The actual storage cell consists of a flip-flop or latch. The designer of standard cell based memories has the choice between many architectural variants. For example, in order to write data to a given address, i.e. to only one row among many rows of flip-flops, one could use flip-flops with an enable feature or flip-flops in conjugation with clock gates. Similarly, to read data from a given address, one could use flip-flops with multiplexers or tri-state buffers at their outputs. Fig. 1 shows an example of a standard cell based memory. A big variety of standard cell based memories has already been designed by the author. In order to test a big number of memories in an exhaustive way, it is convenient to have test structures on the same chip as the memories, rather than feeding a lot of test data through slow I/O pads. Because our main goal is to optimize the memories for low power consumption, we are interested in how they behave when scaling down their supply voltage. The test chip requires at least two separate power supplies: one supply for the memories, which we want to scale down, and another one for the test structures, which remains at the typical voltage (1.2V for UMC 130nm technology) in order to guarantee correct operation. First of all, you develop an understanding for what kind of errors can possibly arise in the memories. Errors can be due to manufacturing errors, operation at low supply voltage, noise, etc. You then develop test vectors which are capable of revealing these errors and propagating them to the outputs of the memory under test. Given a set of test vectors, you design a test vector generator, in a top-down digital VHDL design flow. Next, you design a response comparator which compares actual data read back from the memory with expected responses, i.e. the test vectors which have previously been written into the memory. Finally, you conceive a bidirectional interface for the test chip to communicate with the outside world. In fact, test control signals must be fed to the chip, and the chip must be able to indicate the outcome of a given test, i.e. it must issue a test protocol





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