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vlsi layout tool magic


Magic is an interactive system for creating and modifying VLSI circuit layouts. With Magic, you use a color graphics display and a mouse to design basic cells and to combine them hierarchically into large structures. Magic is different from other layout editors you may have used. The most important difference is that Magic is more than just a color painting tool: it understands quite a bit about the nature of circuits and uses this information to provide you with additional operations. For example, Magic has built-in knowledge of layout rules; as you are editing, it continuously checks for rule violations. Magic also knows about connectivity and transistors, and contains a built-in hierarchical circuit extractor. Magic also has a plow operation that you can use to stretch or compact cells. Magic has (simple) routing tools that you can use to make the global interconnections in your circuits.

Magic is based on the Mead-Conway “scalable CMOS” style of design (from the classic textbook by Carver Mead and Lynn Conway), using “lambda-based” dimensions. Whereas foundries specify detailed dimensions (physical dimensions, that is, in microns) for a specific fabrication process, “lambda” units are dimensionless. When layout data are converted to a CIF or GDS file to send to the foundry for chip fabrication, the lambda units are converted to physical units at a scale appropriate for the intended fabrication process. The advantage of scalable CMOS is that the same design can be fabricated on a different fabrication process by generating a different output file, converting the lambda units to physical dimensions at a different scale. The disadvantage of scalable CMOS is that to ensure a valid layout meeting all the design rules of all the processes, each lambda dimension must meet the worst-case design rule requirements for every process intended to be compatible with the technology file. Unless the processes are completely compatible with one another and processes at different feature sizes scale exactly, then the lambda rules cannot ever specify the densest possible widths and spacings of materials.

Independently of attempting to encompass multiple fabrication processes with one design style, lambda-based rules also attempt to simpify design style by describing most geometry with small integer units that do not vary from process to process. The foundation of this idea is the fact that process “feature sizes” are (nearly always) derived from the most critical dimension for digital circuit speed, the gate length of a MOS transistor. The “feature size” of the process is equal to the minimum gate length (or minimum nFET gate length, in the case that n and p devices have different minimum length requirements). A “0.18 micron” process is one in which the minimum nFET gate length is 0.18 microns. Lambda-based rules use the gate length as the standard measure. One lambda is equal to 1/2 minimum nFET gate length. For most processes, then, minimum dimensions generally work out to the following:

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