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vlsi layout terms


• Placers: A placer optimizes the placement of cells or devices using physical and logical constraints. Placers are generally designed to work with specific routers; therefore, it is very important to use a placer and router from the
same vendor. This is because the two tools work together to meet the constraints and take advantage of features and information that are known to  both tools.
To understand more about this topic, we will expand on the features and constraints of placers in the sections related to specific levels of design. Once understood, it should be clearer why it is better for a placer and router to work together. As a simple example, a channel router needs channels to route with, so the placer must provide these channels. If not, the world’s best placer may be useless.
In terms of types, there are three basic levels of placers, each having different features and requirements:
Inside cells—transistor and cell placement Inside blocks—cells, blocks, or mixed cell and block placement
Chip level—block-level placement within a floorplanning tool

• Routers: Routers were the first automation tools that were widely used. A router enhances the speed of layout interconnect. At first routers were capable of chip-level routing; they have evolved to handle cell-level routing
today. A router is a must when the complexity of connections is beyond the capabilities and efficiency of a manual approach.
Layout generation tools include the following:
• Layout editor:Apolygon pusher or layout editor is used to generate polygons
and paths using a graphical user interface. Some of them are very sophisticated
and may include place-and-route functionality.
• Symbolic editor: A symbolic layout editor has the same user interface as a polygon pusher. However, the layout is generated symbolically from a coded or mathematical algorithm that is programmed into the tool. The advantage
of this approach is that the process design rules are used as parameters to the code; therefore, it is easy to generate layout for different processes.
• Device generators: Device generators are used to generate layout devices such as transistors, via arrays, or logic gates. They typically have an extensive graphical user interface and a highly developed macro language. In some
cases the device generator is an enhancement to a layout editor or an independent
tool. Without a placer or a router, device generators have very
limited value for enhancing productivity.
• Compactors: Acompactor automatically optimizes existing layout and is generally
used as an enhancement to an advanced layout editor or symbolic
layout tool. The compactor shrinks or enlarges the width and space between
polygons with a goal of minimizing the layout to the limits of the process
design rules.
• Silicon compilers: Silicon compilers are used to generate layout automatically
by generating transistors, leaf cells and structures using the leaf cells based
on a standard architecture. In general, silicon compilers do not have a graphical
user interface, as they are used to process a large number of structures.
They are developed mostly by and for people with a lot of software
experience.





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