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vlsi interview question-objective type-02


16. A parity bit is (a) used to indicate uppercase letters (b) used to detect errors (c) is the first bit in a byte (d) is the last bit in a byte
17. A 20-bit address bus allows access to a memory of capacity (a) 1 Mb (b) 2 Mb (c) 32Mb (d) 64 Mb
18. A 32-bit address bus allows access to a memory of capacity (a) 64 Mb (b) 16 Mb (c) 1 Gb (d) 4 Gb
19.Clock speed is measured in (a) bits per second (b) baud (c) bytes (d) Hertz
20. On-chip cache has (a) lower access time than RAM (b) larger capacity than off chip cache (c) its own data bus (d) become obsolete
21. An FPU (a) makes integer arithmetic faster (b) makes pipelining more efficient (c)increases RAM capacity (d) makes some arithmetic calculations faster
22. Pipelining improves CPU performance due to
(a) reduced memory access time (b) increased clock speed (c) the introduction of parallellism (d) additional functional units
23. The system bus is made up of (a) data bus (b) data bus and address bus (c) data bus and control bus (d) data bus, control bus and address bus
24. The von Neumann bottleneck is due to (a) mismatch in speed between secondary and
primary storage (b) mismatch in speed between the CPU and primary storage (c) slow speed
of I/O devices (d) low clock speeds
25. Cache memory enhances (a) memory capacity (b) memory access time (c) secondary
storage capacity (d) secondary storage access time
26. Cache memory (a) has greater capacity than RAM (b) is faster to access than CPU
registers (c) is permanent storage (d) faster to access than DRAM
27. A machine cycle refers to (a) fetching an instruction (b) clock speed (c) fetching,
decoding and executing an instruction (d)executing an instruction
28. CISC machines (a) have fewer instructions than RISC machines (b) use more RAM than
RISC machines (c) have medium clock speeds (d) use variable size instructions
29. RISC machines typically (a) have high capacity on-chip cache memories (b) have fewer
registers than CISC machines (c) are less reliable than CISC machines (d) typically execute
1 instruction per clock cycle.
30. CPU performance may be measured in (a) BPS (b) MIPS (c) MHz (d) VLSI





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