vlsi interview question


VLSI Interview Questions and answers
1. Go through VLSI book from beginning to the end
2. If possible solve all the problems at the end of the chapter
3. Most basic question is draw digital gates using transistors, difference between bipolar and cmos , analog and digital
4. Go through the details on your project
5. Refresh your circuit theory, basic LCR circuit , transfer function , ..
Additional questions can be reffered as

1. before going for these types of interview questions , study any good vlsi book
2. measure your capability by your shelf, you can go to any chapter end questions and see how many quCestions you can solve
3. for experienced professionals prepare one of your projects thoroughly, most common question for vlsi experienced professionals is explain one of the projects , remember you have to explain relevant experience which are suitable for the job requirement
4. for fundamentals you may be asked on deep sub micron technology , channel length modulation, mos characteristics, noise , ..

vlsi interview questions and answers

1) Give two ways of converting a two input NAND gate to an inverter
2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
4) Give a circuit to divide frequency of clock cycle by two
5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied?
9) Give the truth table for a Half Adder. Give a gate level implementation of the same.
10) Draw a Transmission Gate-based D-Latch.
11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12) How do you detect if two 8-bit signals are same?
13) How do you detect a sequence of “1101? arriving serially from a signal line?
14) Design any FSM in VHDL or Verilog

additional questions

what is your roles and responsibilities in that project
what all cores where present in that chip
what is the technology like 130,90,65,45nm
what is the clock-frequency
how many clock-domains
what is the voltage value
what is the macro-count
what is the flip-flop count
what are the various analog macros
how many pads were there
what is your skew you had achieved
what is your insertion delays
what is your pll jitter
how did you model your uncertainities or variations
how many power-domains were there
did you have multi-VDD
if you had multi-VDD how did you handle insertion of level-shifters
what is the SSN(simultaneous switching noise) pad ratios used in your design.
how did you prevented noise in your chip
how many placeable instances
what is the cell-row utilization
is your design pad-limited or core-limited
did you multiplexed your pads
what type of package wafer bond or flip-chip
if flip-chip how did you distributed power bumps any special strategy
how many metal layers in your technology
did you used in house library or from any vendor
what is the die-area of your chip

vlsi interview questions and answers

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  1. VLSI Interview Questions and answers

    vlsi interview question

  2. VLSI Interview Questions and answers

    vlsi interview question

  3. deepchand jaiswal

    Vrespected sir/madam,
    i am MTech VLSI Design final year student,
    please help me for selection of THESES topics
    my email is deepchand55@gmail.com,
    mob +919713279423

    • Guru

      Hi Deepchand,
      For your thesis your guide should be well aware of the topic selected , few ideas of the thesis
      VLSI IMPLEMENTATION OF ANALOG SIGNAL PROCESSING BLOCKS
      Estimating Power Consumption in FPGA Chips
      power management of rfid tags
      latest image sensor design
      DSP chips review,
      Guru

      • Guru

        few more proposed vlsi projects for you
        Modeling System Design Language Basic Blocks in VHDL
        Modeling Telecommunication Protocols and Interfaces
        VLSI circuit for an eight bit CPU was designed
        VLSI circuit for a combinational lock with external keyboard
        VLSI circuit for a keyboard door lock
        Analysis & Synthesis of Testable Core Based Memory
        Analog HDL Simulation & Synthesis
        Hardware Model Code Coverage
        Vital Gate Level Cycle Based Simulation
        FPGA Macro Cell Generator
        Reconfigurable Computing Using Linear Systolic Array Processors
        RTL Cycle Based Simulation
        Back Annotation of Gate and Transistor Level Timing Information to Behavioral Level Description in Verilog HDL
        Guru

  4. deepchand jaiswal

    Vrespected sir/madam,
    i am MTech VLSI Design final year student,
    please help me for selection of THESES topics

    my email is deepchand55@gmail.com,
    mob +919713279423

    • Guru

      Hi Deepchand,
      For your thesis your guide should be well aware of the topic selected , few ideas of the thesis
      VLSI IMPLEMENTATION OF ANALOG SIGNAL PROCESSING BLOCKS
      Estimating Power Consumption in FPGA Chips
      power management of rfid tags
      latest image sensor design
      DSP chips review,

      Guru

      • Guru

        few more proposed vlsi projects for you
        Modeling System Design Language Basic Blocks in VHDL
        Modeling Telecommunication Protocols and Interfaces
        VLSI circuit for an eight bit CPU was designed
        VLSI circuit for a combinational lock with external keyboard
        VLSI circuit for a keyboard door lock
        Analysis & Synthesis of Testable Core Based Memory
        Analog HDL Simulation & Synthesis
        Hardware Model Code Coverage
        Vital Gate Level Cycle Based Simulation
        FPGA Macro Cell Generator
        Reconfigurable Computing Using Linear Systolic Array Processors
        RTL Cycle Based Simulation
        Back Annotation of Gate and Transistor Level Timing Information to Behavioral Level Description in Verilog HDL
        Guru

  5. Amar

    I am fresher m.tech from India, Can I get help for finding out the vlsi companies in India ?
    Amar
    vlsi job applicant

    • Guru

      There are so many MNC and Indian companies are in India, some of the companies are listed here
      ./vlsi-companies-in-india
      Guru

  6. Amar

    I am fresher m.tech from India, Can I get help for finding out the vlsi companies in India ?
    Amar
    vlsi job applicant

    • Guru

      There are so many MNC and Indian companies are in India, some of the companies are listed here
      ./vlsi-companies-in-india

      Guru

  7. Guru

    Are you looking for VLSI , ASIC Interview questions and answers
    ./vlsi-interview-question

  8. Guru

    Are you looking for VLSI , ASIC Interview questions and answers
    ./vlsi-interview-question

  9. job applicant

    Thanks a lot, these helped me a lot for the preparation for my job interview

  10. job applicant

    Thanks a lot, these helped me a lot for the preparation for my job interview

  11. Guru

    Thanks everybody for the contribution on this vlsi interview questions and answers

  12. Guru

    Thanks everybody for the contribution on this vlsi interview questions and answers

  13. Guru

    few collected vlsi interview questions with answer
    Why power stripes routed in the top metal layers?
    The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.
    Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?
    Answer:
    This approach allows routability of the design and better usage of routing resources.
    What are several factors to improve propagation delay of standard cell?
    Answer:
    Improve the input transition to the cell under consideration by up sizing the driver.
    Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
    If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.
    How do you compute net delay (interconnect delay) / decode RC values present in tech file?
    What are various ways of timing optimization in synthesis tools?
    Answer:
    Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.
    Less number of logics between Flip Flops speedup the design.
    Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.
    Better selection of design ware component (select timing optimized design ware components).
    Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.
    What would you do in order to not use certain cells from the library?
    Answer:
    Set don’t use attribute on those library cells.
    How delays are characterized using WLM (Wire Load Model)?
    Answer:
    For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.
    Fanout vs net length is tabulated in WLMs.
    Values of unit resistance R and unit capacitance C are given in technology file.
    Net length varies based on the fanout number.
    Once the net length is known delay can be calculated; Sometimes it is again tabulated.
    What are various techniques to resolve congestion/noise?
    Answer:
    Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.
    Noise can be reduced by optimizing the overlap of nets in the design.
    Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
    Answer:
    No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??
    How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?
    Answer:
    Better skew targets and insertion delay values provided while building the clocks.
    Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.
    For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

  14. Guru

    few collected vlsi interview questions with answer

    Why power stripes routed in the top metal layers?
    The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

    Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

    Answer:
    This approach allows routability of the design and better usage of routing resources.
    What are several factors to improve propagation delay of standard cell?
    Answer:
    Improve the input transition to the cell under consideration by up sizing the driver.
    Reduce the load seen by the cell under consideration, either by placement refinement or buffering.
    If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.
    How do you compute net delay (interconnect delay) / decode RC values present in tech file?

    What are various ways of timing optimization in synthesis tools?
    Answer:
    Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.
    Less number of logics between Flip Flops speedup the design.
    Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.
    Better selection of design ware component (select timing optimized design ware components).
    Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.
    What would you do in order to not use certain cells from the library?
    Answer:
    Set don’t use attribute on those library cells.
    How delays are characterized using WLM (Wire Load Model)?
    Answer:

    For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.

    Fanout vs net length is tabulated in WLMs.

    Values of unit resistance R and unit capacitance C are given in technology file.
    Net length varies based on the fanout number.
    Once the net length is known delay can be calculated; Sometimes it is again tabulated.
    What are various techniques to resolve congestion/noise?
    Answer:
    Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.
    Noise can be reduced by optimizing the overlap of nets in the design.
    Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?
    Answer:
    No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??
    How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?
    Answer:
    Better skew targets and insertion delay values provided while building the clocks.
    Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.
    For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

  15. b

    combination

  16. b

    combination

  17. VLSI Course - Zebros India Chennai

    Learn VLSI Course in 1,00,000 Mins
    @ Zebros India , Chennai
    contact : 044 45511910
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  18. VLSI Course - Zebros India Chennai

    Learn VLSI Course in 1,00,000 Mins

    @ Zebros India , Chennai

    contact : 044 45511910

    http://www.zebrosindia.com

  19. Interview Questionnaire

    What is VLSI. I mean is it related to software programming? Please help me ..thanks
    Answer:VLSI stands for very large scale integration, it is combination of electronics, software go to
    ./vlsi-design for knowing more details.

  20. Interview Questionnaire

    What is VLSI. I mean is it related to software programming? Please help me ..thanks
    Answer:VLSI stands for very large scale integration, it is combination of electronics, software go to
    ./vlsi-design for knowing more details.

  21. software interview questions

    Hello,can anybody please provide software interview questions for fresh graduate seeking in Java based job.PLease provide interview questions along with answers also.
    Answer : ./java-interview-questions
    and
    http://www.allapplabs.com/interview_questions/java_interview_questions.htm

  22. software interview questions

    Hello,can anybody please provide software interview questions for fresh graduate seeking in Java based job.PLease provide interview questions along with answers also.

    Answer : ./java-interview-questions
    and
    http://www.allapplabs.com/interview_questions/java_interview_questions.htm

  23. sunrise

    hi could you please suggest a good book for a newbie interested in vlsi…
    ready to learn , eager to excel..pls if possible mail me at notknownphilospher[at]yahoo[dot]com
    Answer: Go to ./vlsi-book which have good list on vlsi books so also free lecture notes on vlsi

  24. sunrise

    hi could you please suggest a good book for a newbie interested in vlsi…
    ready to learn , eager to excel..pls if possible mail me at notknownphilospher[at]yahoo[dot]com

    Answer: Go to ./vlsi-book which have good list on vlsi books so also free lecture notes on vlsi

  25. Guru

    VLSI Interview Questions and Answers
    VLSI Interview Questions and Answers.

  26. Guru

    VLSI Interview Questions and Answers
    VLSI Interview Questions and Answers.

  27. gowthami

    its really very good collection of vlsi……
    iam going to appear for bharat electronics limited(BEL) written exam will u please kindly give me some links to appear these kind of exams…..
    Gowthami, lets us know what is the position, we may help you for getting sample interview questions

  28. gowthami

    its really very good collection of vlsi……
    iam going to appear for bharat electronics limited(BEL) written exam will u please kindly give me some links to appear these kind of exams…..

    Gowthami, lets us know what is the position, we may help you for getting sample interview questions

  29. Guru

    ./vlsi-interview-questions vlsi interview questions and answers

  30. Guru

    ./vlsi-interview-questions vlsi interview questions and answers

  31. vipin

    some vlsi questions with answers can be found at:
    http://vhdlguru.blogspot.com/2010/04/here-are-some-common-interview.html

  32. vipin

    some vlsi questions with answers can be found at:
    http://vhdlguru.blogspot.com/2010/04/here-are-some-common-interview.html

  33. Guru

    vlsi interview questions and answers includes asic interview , verilog interview questions and answers

  34. Guru

    vlsi interview questions and answers includes asic interview , verilog interview questions and answers

  35. Guru

    Thanks for your comment
    visit ./vlsi-companies-in-india

  36. Guru

    Thanks for your comment
    visit ./vlsi-companies-in-india

  37. vlsi job applicant

    VLSI Interview questions, asic interview questions, soc interview questions, all in one place
    If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
    Define hash/ @array in perl.
    Using TCL (Tool Command Language, Tickle) how do you set variables?
    What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
    What are nanoroute options for search and repair?
    What were your design skew/insertion delay targets?
    How is IR drop analysis done? What are various statistics available in reports?
    Explain pin density/ cell density issues, hotspots?
    How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
    What is the command for setting multi cycle path?
    If hold violation exists in design, is it OK to sign off design? If not, why?
    How are timing constraints developed?
    Explain timing closure flow/methodology/issues/fixes.
    Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
    Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
    With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
    What are synthesis strategies to optimize timing?
    Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

  38. vlsi job applicant

    VLSI Interview questions, asic interview questions, soc interview questions, all in one place
    If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
    Define hash/ @array in perl.
    Using TCL (Tool Command Language, Tickle) how do you set variables?
    What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
    What are nanoroute options for search and repair?
    What were your design skew/insertion delay targets?
    How is IR drop analysis done? What are various statistics available in reports?
    Explain pin density/ cell density issues, hotspots?
    How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
    What is the command for setting multi cycle path?
    If hold violation exists in design, is it OK to sign off design? If not, why?
    How are timing constraints developed?
    Explain timing closure flow/methodology/issues/fixes.
    Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
    Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
    With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
    What are synthesis strategies to optimize timing?
    Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?