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vlsi interview question


VLSI Interview Questions and answers
1. Go through VLSI book from beginning to the end
2. If possible solve all the problems at the end of the chapter
3. Most basic question is draw digital gates using transistors, difference between bipolar and cmos , analog and digital
4. Go through the details on your project
5. Refresh your circuit theory, basic LCR circuit , transfer function , ..

Additional questions can be reffered as

1. before going for these types of interview questions , study any good vlsi book
2. measure your capability by your shelf, you can go to any chapter end questions and see how many quCestions you can solve
3. for experienced professionals prepare one of your projects thoroughly, most common question for vlsi experienced professionals is explain one of the projects , remember you have to explain relevant experience which are suitable for the job requirement
4. for fundamentals you may be asked on deep sub micron technology , channel length modulation, mos characteristics, noise , ..

vlsi interview questions and answers

1) Give two ways of converting a two input NAND gate to an inverter
2) Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
3) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
4) Give a circuit to divide frequency of clock cycle by two
5) Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6) Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
7) The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? What are the different Adder circuits you studied?
9) Give the truth table for a Half Adder. Give a gate level implementation of the same.
10) Draw a Transmission Gate-based D-Latch.
11) Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
12) How do you detect if two 8-bit signals are same?
13) How do you detect a sequence of “1101? arriving serially from a signal line?
14) Design any FSM in VHDL or Verilog

additional questions

what is your roles and responsibilities in that project
what all cores where present in that chip
what is the technology like 130,90,65,45nm
what is the clock-frequency
how many clock-domains
what is the voltage value
what is the macro-count
what is the flip-flop count
what are the various analog macros
how many pads were there
what is your skew you had achieved
what is your insertion delays
what is your pll jitter
how did you model your uncertainities or variations
how many power-domains were there
did you have multi-VDD
if you had multi-VDD how did you handle insertion of level-shifters
what is the SSN(simultaneous switching noise) pad ratios used in your design.
how did you prevented noise in your chip
how many placeable instances
what is the cell-row utilization
is your design pad-limited or core-limited
did you multiplexed your pads
what type of package wafer bond or flip-chip
if flip-chip how did you distributed power bumps any special strategy
how many metal layers in your technology
did you used in house library or from any vendor
what is the die-area of your chip

vlsi interview questions and answers

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  1. Guru

    vlsi interview questions and answers includes asic interview , verilog interview questions and answers

  2. Guru

    Thanks for your comment
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  3. vlsi job applicant

    VLSI Interview questions, asic interview questions, soc interview questions, all in one place
    If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
    Define hash/ @array in perl.
    Using TCL (Tool Command Language, Tickle) how do you set variables?
    What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
    What are nanoroute options for search and repair?
    What were your design skew/insertion delay targets?
    How is IR drop analysis done? What are various statistics available in reports?
    Explain pin density/ cell density issues, hotspots?
    How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
    What is the command for setting multi cycle path?
    If hold violation exists in design, is it OK to sign off design? If not, why?
    How are timing constraints developed?
    Explain timing closure flow/methodology/issues/fixes.
    Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
    Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
    With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
    What are synthesis strategies to optimize timing?
    Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?



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