vlsi interview 3
Logic design questions, memory Interview question
1. Multiples of 5 detector on an infinite width shift register. Also multiples of 6 detector.
2. Divide by 2, Divide by 3 circuit with equal duty cycle.
3. Frequency multipliers. Delay the clock using multiphase DLL, pll etc , and then use XORs.
4. Edge detectors.
5. Given Two 4 bit nos
B = 1100
HOW DO YOU XOR them using minimum number of gates? How do you nand them? How do your or them? (Hint: 4:1 Muxes)
6. How many 4:1 mux do you need to design a 8:1 mux?
7. Traffic Light controller State Machine (Highway/Farmway intersection).
8. D-Word, Q-word?
9. Size of the biggest design you have done. Did u have multiple clock domains? How was clock-crossing accomplished. Synchronizers, metastability, determinism?
10.Define Moore, Mealy state machines. Which ones are good for timing?
11.IScan, Bscan? Provide example applications. How do u make reset controllable from toplevel.
12.Design a FSM to detect 10110. What is the minimum # of flops required?
13.Prime # detector
14.Prime # counter
15.Digital one shot (merging pulses to one pulse).
16.Pulse clipper (or a return to zero ) circuit. Design a clock to pulse circuit in Verilog / hardware gates.
17. Design a simple circuit based on combinational logic to double the output frequency.
18.Implement comparator that compares two 2-bit numbers A and B. The comparator should have 3 outputs: A > B, A < B, A = B. (Reduce the equations using Karnaugh Map) Do it two ways: - using combinational logic; - using multiplexers. Write HDL code for your schematic at RTL and gate level. 19.What types of flip-flops do you know? 20. Implement D- latch from – RS flip flop; – multiplexer. 21. How to convert D-latch into JK-latch and JK-latch into Dlatch? 22. You have two counters to 16, built from negedge D- FF . First circuit is synchronous and second is “ripple” (cascading). Which circuit has a less propagation delay? 23. What is the difference between flip-flop and latch? Write an HDL code for their behavioral models. 24. What is the max clock frequency the circuit can handle ? T_setup= 6nS T_hold = 2nS T_propagation = 10nS 25. To enter the office people have to pass through the corridor. Once someone gets into the office the light turns on. It goes off when none is present in the room. There are two registration sensors in the corridor. Build a state machine diagram and design a circuit to control the light. 26. Design a 2bit up/down counter with clear using gates. (No verilog or vhdl) 27. We have a fifo which clocks data in at 100mhz and clocks data out at 80mhz. On the input there is only 80 data in any order during each 100 clocks. In other words, a 100 input clock will carry only 80 data and the other twenty clocks carry no data (data is scattered in any order). How big the fifo needs to be to avoid data over/underrun. 28. Design a state-machine (or draw a state-diagram) to give an output ‘1’ when the # of A’s are even and # of B’s are odd. The input is in the form of a serial-stream (one-bit per clock cycle). The inputs could be of the type A, B or C. At any given clock cycle, the output is a ‘1’, provided the # of A’s are even and # of B’s are odd. At any given clock cycle, the output is a ‘0’, if the above condition is not satisfied. 29. To detect the sequence “abca” when the inputs can be a b c d. 30. Given a function whose inputs are dependent on its outputs. Design a sequential circuit. 31. Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1. 32. Minimize: S= A’ + AB 33. Given a boolean equation draw the transistor level circuit. 34. What is the function of a D-flipflop, whose inverted outputs are connected to its input? 35.Sender sends data at the rate of 80 words / 100 clocks Receiver can consume at the rate of 8 words / 10 clocks Calculate the depth of FIFO so that no data is dropped. Assumptions: There is no feedback or handshake mechanism. Occurrence of data in that time period is guaranteed but exact place in those clock cycles is indeterminate. 36.Optical sensors A and B are positioned at 90 degrees to each other as shown in Figure. Half od the disc is white and remaining is black. When black portion is under sensor it generates logic 0 and logic 1 when white portion is under sensor. Design Direction finder block using digital components (flip flops and gates) to indicate speed. Logic 0 for clockwise and Logic 1 for counter clockwise. Cannot assume any fixed position for start. 37.Will this design work satisfactorily? Assumptions: thold = tsetup = tclock_out = tclock_skew = 1ns. After reset A = 0, B = 1 38. How to synchronize control signals and data between two different clock domains? 39.Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads. 40. In what cases do you need to double clock a signal before presenting it to a synchronous state machine? 41. How many bit combinations are there in a byte? 42. What are the different Adder circuits you studied? 43. Give the truth table for a Half Adder. Give a gate level implementation of the same. 44.Convert 65(Hex) to Binary 45.Convert a number to its two’s compliment and back. 46.What is the 1’s and 2’s complement of the decimal number 25. 47.VHDL/Verilog sensitivity list? Any other techniques to accomplish the same thing? 48.Difference between signal/variable. 49.Karnaugh Map. Given an equation (eg: X + X’Y) reduce. do you have soft resets do you synchronous your resets or not do you have latches in your chip how many power domains do you have what is the supply pad voltage do you used diodes to eliminate ESD how many layers do you do power-routing what is the layers you use for clock-routing do you do anything special for special nets in routing phase did you do routing timing driven or not did you enable signal integrity while routing did you validate SI based STA using PT-SI or some other tool what is the extra margin di dyou kept during synthesis phase how many ECO’s do you faced to close the timing or functional verification do you used to run formal verification to validate the handover RTL and netlist are fine did you checked antenna violation did you qualify your chip with GLS(gate level simulation) what is the package frame number how did you performed timing budgetting anything special you did to increase the yield how did you estimate your power-strips and meshes widths do you have different analog ground and digital ground if so for any reason or not do you short analog and digital grounds what is the type of mbist controllers you used did you run capture mode simulations do you used any test-compression logic in your chip what is your fanout tree count