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VLSI implementation of a bi processor architecture


This paper presents an architecture for the multiresolution coding of pictures. A VLSI implementation has been realized and can achieve a peak performance of about 500 MOPS. The architecture consists in 2 processors whose complementarity enables to avoid any wait cycles during the execution so that the available computation power is continuously used. Moreover, the circuit has a total programmability with respect to the used lters and the picture format; it also has the possibility to take edge e ects into account and therefore improve the coding performances. The circuit can be used in the coding as well as in the decoding. Many image compression schemes using the subband coding have been proposed for some years . The subband coding is closely related to the multiresolution decomposition of a picture and has many advantages with regard to the DCT-based techniques. Associated to an adapted entropy coder, it can also achieve higher compression ratios. Moreover, the multiresolution transform is close to the human visual system and achieves a high perceptual quality. The multiresolution has thus very attractive and interesting features, but up to now, it is not part of any standardized coding systems. Many parameters can still be tuned and optimized in order to achieve the best performances in the di erent application elds. This optimization and research often call for real-time tests that can not b e easily performed without dedicated VLSI. This paper proposes such a programmable VLSI architecture.

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