VLSI Cell Synthesis

There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary ratioed logic families can be highly irregular, with complex diffusion sharing and nontrivial routing. Traditional digital cell layout synthesis tools derived from the highly stylized “functional cell” style break down when confronted with such circuit topologies. These cells require a full-custom, two-dimensional layout style which currently requires skilled manual design. In this work we propose a methodology for the synthesis of such complex noncomplementary digital cell layouts. We describe a new algorithm which permits the concurrent optimization of transistor chain placement and the ordering of the transistors within these diffusion-sharing chains. The primary mechanism for supporting this concurrent optimiza-tion is the placement of transistor subchains, diffusion-break-free components of the full transistor chains. When a chain is reordered, transistors may move from one subchain (and therefore one placement component) to another. We will demonstrate how this permits the chain ordering to be optimized for both intra-chain and inter-chain routing. We combine our placement algorithms with third-party routing and compaction tools, and present the results of a series of experiments which compare our technique with a commercial cell synthesis tool. These experiments make use of a new set of benchmark circuits which provide a rich sample of representative examples in several noncomplementary digital logic families.

Library cells are the lowest level of the digital VLSI design hierarchy. Clearly, the quality of cells in a given library has a direct impact on the quality of the final design. The cells must be designed to be compact and fast, with minimized power and parasitics, and with careful attention paid to requirements on the physical architecture of the cells as viewed by the higher-level placement and routing tools. Automated synthesis techniques have found limited application at the cell level because existing tools are unable to match the quality of human designed cells. For this reason cells are often designed by hand, requiring a significant investment in manpower.

An additional difficulty lies in the fact that the lifetime of a typical cell li-brary may be as short as 1 or 2 years. Compaction techniques may be used to migrate a cell library to a new process technology if little more than a linear shrink is required, but this is unlikely to extend the lifetime for more than one or two process generations before the loss in performance necessitates a com-plete redesign of the library. These problems are only becoming worse as device geometries shrink into the deep submicron regime.

In order to account for deep submicron effects when designing large chips, ever closer interaction is required between front-end logic synthesis tools and back-end placement and routing tools, power and delay optimization tools, and parasitic extraction tools. In order to enable this interaction, cell libraries must become more flexible. Multiple versions of each cell with different drive strengths are required. It may even be necessary to support versions of cells in different logic families with different power/delay tradeoffs. In leading-edge integrated circuit designs, static CMOS and dynamic domino CMOS tend to be dominant, but there is a growing need for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL) and Pass Transistor Logic (PTL). In addition, synchronizing elements such as latches and flip-flops tend to be designed using custom analog sense amplifier techniques.

In addition to the need for families of cells which are parameterized in terms of their electrical behavior, it has been demonstrated that standard-cell place-ment and routing tools are able to obtain significantly higher routing quality if they have the ability to choose between multiple instances of cells with a wide variety of pin orderings. In one experiment [Lefebvre et al. 1997], an average reduction in the number of routing tracks of 10.8% was demonstrated over five benchmark circuits.

It seems clear that as the number of cells in a typical cell library grows from the hundreds into the thousands, a dramatic increase in designer productivity will be required, necessitating a move toward more automated cell synthesis techniques. Several authors, in fact, advocate a move completely away from static cell libraries as we know them, toward a system which permits the auto-mated synthesis of cells on demand [Lefebvre et al. 1997; Burns and Feldman 1998]. This would permit logic synthesis tools to request specific logic decom-positions, doing away with the traditional technology mapping step; standard-cell and datapath placement and routing tools to request cells with an exact pin ordering; interconnect optimization tools to request cells with specific input and output impedance values; and power optimization tools to request cells, perhaps from one of several different logic families, with specific power/delay tradeoffs. Such an on-demand cell synthesis system will require effort on many fronts:

(1) Automated transistor schematic generation (constraint-driven logic family selection, netlist creation, and transistor sizing);
(2) automated cell geometry synthesis;
(3) automated cell testing and characterization; and (4) development of enabling logic synthesis, placement and routing, and power/delay optimization technology.


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