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techniques for transistor layout matching


1. Use identical finger geometries.
Transistors of different widths and lengths match very poorly. Even minimally matched devices must have identical channel lengths. Most matched transistors require relatively large widths and are usually divided into sections, or fingers. Each of these fingers should have the same width and length as all others. Do not attempt to match transistors of different widths and lengths, because the width and length correction factors, dW and dL, vary substantially from lot-to-lot.

2. Use large active areas.

The active area of an MOS transistor equals the product of its channel width and length. Assuming that all other matching considerations have been addressed, the residual offset due to random fluctuations scales inversely with the square root of device area. Moderate matching usually requires active areas of several hundred square microns,
while precise matching requires thousands of square microns.

3. For voltage matching, keep Vgst small.

The offset voltage of a pair of matched MOS transistors contains a term dependent on device transconductance. This term scales with Vgst, so smaller values of Vgst provide better voltage matching. Reducing the Vgst below O.1V provides little additional benefit because threshold voltage variations begin to dominate the offset equation. Most designers decrease Vgst by using larger W/L ratios because these simultaneously increase the active area of the transistors.

4.For current matching, keep Vgst large.

delta Id / Id = delta k/k + 2delta Vt/Vgst

The current mismatch equation contains a term dependent upon threshold voltage. This term scales inversely with Vgst, so large values of Vgs, minimize its impact upon current matching. Circuits relying upon current matching should maintain a nominal Vgst of at least O.3V. Moderately matched transistors should maintain a nominal Vgst of at least O.5V whenever headroom allows. Precisely matched transistors Thould use the lar

5.Orient transistors in the same direction.

Transistors that do not lie parallel to one another become vulnerable to stress-and tilt-induced mobility variations that can cause several percent variation in their transconductance. This effect is so severe that even minimally matched transistors should lie parallel to one another. Matched transistors, especially those that are not fully self-aligned, should have equal chirality. This condition can be met by ensuring that each transistor contains an equal number of segments oriented in each direction.

6. Place transistors in close proximity.

MOS transistors are vulnerable to gradients in temperature, stress, and oxide thickness. Even minimally matched devices should reside as close as possible to one another. Moderately or precisely matched transistors should be kept next to one another to facilitate common-centroid layout.

7.Keep the layout of the matched transistors as compact as possible.

MOS transistors naturally lend themselves to long, spindly layouts that are extremely vulnerable to gradients. Common-centroid layout cannot entirely eliminate this vulnerability, so the designer should strive to create as compact an arrangement of matched devices as possible. This usually requires that each device be divided into a number of fingers.

8. Where practical, use common-centroid layouts.

Moderately and precisely matched MOS transistors require some form of common-centroid layout. This can often be achieved by dividing each transistor into an even number of fingers and by then arranging these fingers in an interdigitated array. Pairs of matched transistors should be laid out as cross-coupled pairs to take advantage of the superior symmetry of this arrangement.

9. Place dummy segments on the ends of arrayed transistors. Arrayed transistors should include dummy gates at either end. These dummies need not have the same length as the actual gates, but the spacing between the dummy gates and the actual gates must equal the spacing between actual gates. The moat diffusion should extend at least several microns into the dummies to prevent the edge of the dummies from resting on the bird’s beak. The dummy gates should be connected, preferably to a potential that prevents channel formation beneath them. This is most easily achieved by connecting the dummies to the backgate potential.

10. Place transistors in areas of low stress gradients. The stress gradients reach a broad minimum in the center of the die. Any location ranging from the center of the die out halfway to the edges will fall within this broad minimum. Whenever possible, precisely matched transistors should reside within this low-stress area. Moderately and precisely matched transistors should reside at least 25um away from any side of the die. The stress distribution reaches a maximum in the die corners, so avoid placing any matched transistors near corners. PMOS transistors may experience slightly less stress dependence when oriented along [001] directions. This effect is not sufficiently pronounced to justify placing minimally or moderately matched transistors diagonally, but precisely matched transistors might benefit from this unconventional orientation. NMOS transistors should always be oriented horizontally and vertically.

12. Do not place contacts on top of active gate area.

Whenever possible, extend the gate poly beyond the moat and place the gate contacts over thick-field oxide. When this is not possible, minimize the number and size of the gate contacts and place them in the same location on each transistor. Consider placing the gate contacts of high-voltage annular transistors over the fie





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