# Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology

The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

The variations in the parameters of two equally designed devices can be defined as mismatch. And it is seen as a limiting factor for the function and performance of analog circuits. In general, mismatch can be classified into two categories according to the different generating mechanisms: fabricated-related mismatch and ambient-related mismatch.

For the fabricated-related mismatch, there are two more

detailed categories: (1) systematic mismatch; (2) random

mismatch. Manufacturing variations results in device

parameter variations from batch to batch, wafer to wafer

and device to device. Batch-to-batch and wafer-to-wafer

variations are common to all devices in the circuit. So,

they are regarded as the systematic mismatch. And their

effect on the circuit performance can be largely eliminated

by layout techniques such as symmetry constraint.

Therefore, the conventional tools for symmetry constraint

[1]-[4] mainly aim at automatically placing the equally

designed devices symmetrically with respect one or

several common axes in order to eliminate the systematic

mismatch. And we define these tools as geometric

symmetry tools. Unfortunately, the existence of random

mismatch weakens the ability of geometric symmetry tools

in eliminating mismatch. Device-to-device variations

which are defined as the random mismatch are caused by

some unpredictable processes during design and

fabrication phases. And random mismatch will greatly

increase as the size of transistors decreases [12]-[14].

Nowadays, the size of transistor is in the magnitude of

deep-submicron. As a result, the random mismatch will

become more severe. This brings a great challenge for

geometric symmetry tools to guarantee the matching

constraint for the symmetrical devices.

The ambient-related mismatch can be expressed as the

mismatch caused by the ambient factors like thermal

condition and noise distribution. Thermal-induced

mismatch [6]-[8] is an important one in this kind of mismatch. Because of the relatively better thermal conductivity of the silicon [8], the thermal-induced mismatch is often neglected and the analog circuits are assumed as isothermal. However, in the context of SOI, the conductivity of isolating buried oxide is often over two orders of magnitude worse than silicon [9]. Thus, even with the relatively moderate power levels encountered in typical signal path transistors, increases in the channel temperature of tens of degrees due to self-heating effect can be observed [10]. And some of the heat generated by the distinct devices will flow laterally before reaching the substrate. So, the temperatures of these neighboring transistors will also rise. The temperature gradients resulting from self-heating and thermal coupling lead to nonisothermal conditions. Literature [11] is proposed to reduce the temperature gradient on symmetrical devices. However, its optimization objective is the Minimum Average Temperature Gradient (MATG) of all symmetry pairs. This method only aims at temperature optimization and ignores the different mismatch sensitivities of devices for different use and this may still lead to mismatch on some sensitive symmetry pairs