SOC Design methodology
• Technology selection: What kind of process will be used? In the case of embedded
memory, perhaps a blend process will do it.
• Type of board on which the chip will be assembled: From this it may be possible
to determine the packaging type, footprint, die size, price, pin positions and
assignment, and power consumption limitations.
• Availability of core/blocks internally or on the external market sold by vendors: Are
they soft or hard cores?
• Libraries available for the chosen process: Are they silicon proven? What power
consumption, speed, and tools are they compatible with?
• Levels of testability to be addressed in the design: This is another hot topic of the
year—design for testability (DFT).
• Limitations of the manufacturing process: Time frame, special layers, reticle limitations,
packaging limitations, etc.
• Reliability of the chosen process: Is it experimental, first-time trial, proven over
a few working chips?