DESIGN ISSUES OF RFICs in TRANSCEIVER
RF-transceiver chip can generally divided into two parts transmitter and receiver. The choice of the architecture for transmitter and receiver is difficult for a designer among the trade off parameters. The chip consists of LNA, down converting mixer, IF amplifier, I/Q demodulator, VCO, I/Q modulator, and transmit driver amplifier, Every module should taken care of some critical parameter. Some of the issues are discussed here.
1. Receiver Architecture: The selection of architecture of receiver is a big issue. We have to consider this one very carefully. Rejection of out-of-band blockers is traditionally achieved with the use of superheterodyne down-converter architecture. While this provides robust performance, it requires the use of external SAW filters and two on-chip synthesizer loops; both of which increase cost. Zero-IF architectures do not require external SAW filters, but suffer from DC offset voltages and high ADC dynamic range requirements. For moderate bit-rate radios, Low-IF superheterodyne architectures replace the external SAW filters with on-chip poly-phase filters, thereby avoiding the DC offset and ADC dynamic range difficulties. For all of these architectures, standard, quadrature, and double-quadrature circuit realizations have different levels of robustness.
2. Transmitter Architecture: The transmitter can be realized as a traditional superheterodyne or as a direct modulation architecture, and either as an image reject or standard architecture. But we should chose one power efficient architecture.
3. Low Noise figure LNA: On the receive side, the incoming signal is usually at a very low level; hence you need an LNA that has good power gain, but a low-noise figure. The Noise figure should be taken more care in this stage compared to gain.
4. Power consumption versus linearity: Trade-off of power consumption versus linearity in the LNA. Assuming a constant efficiency, the more dc powers you put into the LNA, the more linear its operation is, and, therefore, the higher the incoming signal strength it can handle.
5. Interference of undesired Signal: The strong interfering signals coming into the antenna are undesired for the transceiver chip. The desired signal must be processed in the presence of the large interfering tones. Therefore, a very linear amplifier is needed. At the same time, you want to minimize the impact on the battery. Different circuit topologies can accomplish this objective
6. Impedance Mismatch: The source and load of the amplifier are well-defined impedance that must be matched with the succeeding stage. The metal layers connecting two modules is no more simple metal layers as in lower frequency. They are treated as transmission lines. So impedance mismatch due to these metal layers should be taken into great care. Co planar wave-guide factor may come into consideration if the signal line will come closer to ground lines.
7. Non Linearity in down converting mixer: Design trade-off involving power consumption versus linearity is also found in the down converting mixer. The linearity in the receiver is only as good as its weakest link. Therefore, efficient linearity is required in every block of the receive chain, and power consumption must be minimized in every block. An active mixer topology received the approval in this design because it provides efficient linearity, power gain, and medium power consumption. A bit more power is consumed in the mixer in order to get more conversion gain and linearity in the system, thus achieving a happy balance.
8. Constant Signal Power: The modulation scheme required by a particular system determines the choice of IF amplifier and demodulator. In some cases, you can have a log amplifier with a received signal strength indicator (RSSI), or you can use an automatic gain control (AGC) amplifier with an I/Q demodulator, which we utilized in this RF ASIC design. In either case, you??re dealing with a wide range of signal powers, and you need a constant output level. When the input signal is very high, the AGC should be reduced so that you get a constant output. Conversely, if the signal source is far away, the incoming signal can be very low.
9. Linearity of Transmitter: OFDM modulation is very sensitive to the inter-modulation distortion (IMD) that results from mild non- linearity in the RF. Because the sub-carriers are equally spaced, the third-order inter modulation products will appear exactly on top of another carrier. These inter modulation products will contribute to a noise- like cloud surrounding each constellation point, called EVM (Error Vector Magnitude). These will be more prominent for 64 QAM. So For the RF components in the transmitter portion of a transceiver, the linearity requirement must be met at reasonably high power levels. With the associated requirement for high efficiency, this places extreme design challenges upon the architectural realization.
10. Large Peak to Average Power ratio of Transmitter: OFDM Modulation scheme needs very large peak to average power ratio. This needs power amplifier should provide less RF Power between peaks given by PAPR. The peak power level determines the DC Power dissipation. So the dc power dissipation will increase to achieve this large PAPR. This high PAPR requires highly linear upconverters. This means that the up converter must have a high-level compression point, which also results in high dc power consumption.
11. Phase Noise: Maintaining sufficiently low phase noise levels close to LO frequency becomes extremely important in achieving low bit rate performance in an OFDM modem. As in the case inter modulation, a modest increase in the BER for each of the carrier can result in a dramatic increase in the cumulative error rate over the packets. Thus the phase noise must be carefully taken for an OFDM system.
12. Phase Noise of Synthesizer: In any LO synthesizer, the close- in phase noise is composed of the frequency multiplied crystal reference phase noise, phase noise due to the synthesizer circuits (charge pump, phase/frequency comparator, digital dividers), and the voltage controlled oscillator (VCO). Of these, the phase noise of an on-chip VCO will dominate, due to the low Q of its spiral inductors. Techniques to improve the Q of the on-chip spirals continue to be reported and include the use of copper as the top metal layer, and trench isolation in the substrate.
13. On Chip Components: on chip passive components, particularly inductors, are much lower quality than the external equivalent. It can be seen, then, that there is a 3-way trade-off between size, power and performance. So we can think of using flip chip inductors or some other way to achieve better quality factor components.
14. These are some of the issues in RFIC design. There are lot more issues in the design and implementation. I had discussed some issues only.
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