power management blocks-supervisory circuit design

Supervisory circuits and battery monitor chips are semiconductor devices that detect and monitor voltage levels in power supplies, microprocessors, and other systems. As protection circuits, they can monitor one or more system parameters simultaneously. When parameter thresholds are exceeded or dangerous conditions exist, supervisory circuits react to protect the monitored system and correct the problem. Supervisory circuits are known by a variety of names, including battery monitors, power supply monitors, supply supervisory circuits and reset circuits. They perform critical functions. For example, one of the basic functions of a microprocessor (┬ÁP) supervisor is to provide power-on-reset (POR) protection to ensure that the processor always starts at the same address during power-up. Without POR, even well-functioning systems can exhibit problems during power-up, power-down, overvoltage, and undervoltage conditions.

Supervisory circuits and battery monitor chips vary in terms of specifications, features, and output options. Some devices can monitor only one system voltage. Others can monitor 2, 3, 4, or 5 system voltages simultaneously. Supervisory circuits and battery monitor chips with a watchdog timer (WDT) automatically detect system anomalies and reset the processor when irregularities occur. Timeouts update the WDT output state automatically, resetting the microprocessor or generating an interrupt. Supervisory circuits and battery monitor chips that can be reset manually are also available. In terms of features, some devices ensure proper operation of the monitored system during power-up or power-down. Others provide protection during undervoltage or brownout conditions. Power failure warnings notify users when the power fails on the monitored system, or when battery levels are low. Output options for supervisory circuits and battery monitor chips include open drain, inversion, non-inversion, active-low, and active-high. Open-drain outputs are connected internally to the drain of a field-effect transistor. Inversion outputs are inverted with respect to the input voltage. Non-inversion outputs are in phase with the input voltage.