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Power Aware Verification Web Seminar mentor graphics


Mar 2, 2010
9:30 AM – 10:15 AM Europe/London
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Mar 2, 2010
1:00 PM – 1:45 PM Europe/London
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Overview
With total power consumption of an IC now one of the major design constraints, design teams have started to adopt low power design techniques (e.g. Power Gating with/ without retention, Multi Voltage Multi Supply, Adaptive Voltage and Frequency scaling etc) in order to meet their power budgets.

The use of these low power design techniques introduces, among other things, verification challenges since new digital functionality has to be added in order to control the voltage of the power sources in order to reduce total power consumption including leakage and switching power components.

Often times, there is a software component that forms part of the overall low power design which must be verified as well. Until recently, verification of low power designs were done using adhoc practices that did not scale across projects in an organization..

In this session we will look at how new standards, verification tools and techniques can be applied to allow low power designs being verified much earlier at the RTL including the software components.

What You Will Learn
Overview of the Low power design techniques
Specification of low power design architecture in an SoC using research 1801 UPF
Low power bugs that could be introduced as a result of adopting Low power design techniques
Early verification of low power designs at RTL leveraging power aware simulation tools and static checks

source http://www.mentor.com/products/fv/events/power-aware-verification-webinar?clp=1&contactid=1&PC=L&c=2010_02_19_ttt_power_aware_verification_web_seminar_





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