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PLL research papers


Phase-Locked Loops Demystified,
Chip Estimate’s IP Connections Newsletter article by John Maneatis and Eskinder Hailu

Selecting PLLs for ASIC Applications Requires Tradeoffs,
2004 FSA Semiconductor IP Workshop paper by John Maneatis

Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,
research Journal of Solid-State Circuits paper by John Maneatis
(
2003 ISSCC 24.2 presentation slides for this paper)

Hidden Complexities of PLLs Are Revealed,
Integrated System Design article by John Maneatis

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,
research Journal of Solid-State Circuits paper by John Maneatis
(
1996 ISSCC 8.1 presentation slides for this paper)

Precise Delay Generation Using Coupled Oscillators,
research Journal of Solid-State Circuits paper by John Maneatis
(
1993 ISSCC 7.5 presentation slides for this paper)





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