PLL basics

PLL Frequently asked question

Q.How do I minimize lock time?
Q. A.By i ncr eas i ng t he PFD f r e que nc y .The PFD f r equenc y determines the rate at which a comparison is made between the VCO/N and the reference signal.Increasing the PFD frequency increases the update of the charge pump and reduces lock time. It also allows the loop bandwidth to be widened.

Q.What is a PLL Synthesizer?
Q. A.A frequency synthesizer allows the designer to generate a variety of output frequencies as multiples of a single reference frequency. The main application is in generating local oscillator (LO) signals for the up-and down-conversion of RF signals. The synthesizer works in a phase-locked loop (PLL),where a phase/frequency detector (PFD)compares a fed back frequency with a divided-down ver sion of the reference frequency (Figure 1).The PFD ’s output current pulses are fi ltered and integrated to generate a voltage.This voltage drives an external voltage-controlled oscillator (VCO)to increase or decrease the output frequency so as to drive the PFD ’s average output towards zero.

Q.What are the key performance parameters to be considered in selecting a PLL synthesizer?
Q. A.The maj or ones ar e:phas e noi s e,r ef er ence s pur s ,and l ock t i me. Phase Noise :For a carrier frequency at a given power level, the phase noise of a synthesizer is the ratio of the carrier power to the power found in a 1-Hz bandwidth at a defi ned frequency offset (usually 1 kHz for a synthesizer).Expressed in dBc/Hz, the in-band (or close-in)phase noise is dominated by the synthesizer;the VCO noise contribution is high-pass fi ltered in the closed loop. Reference Spurs :These are ar tif acts at discrete offset frequencies generated by the internal counters and charge pump operation at the PFD frequency.These spurs will be increased by mismatched up and down currents from the charge pump,charge-pump leakage,and inadequate decoupling of supplies.The spurious tones will get mixed down on top of the wanted signal and decrease receiver sensitivity. Lock Time :The lock time of a PLL is the time it takes to jump from one specifi ed frequency to another specifi ed frequency within a given frequency tolerance.The jump size is normally deter mined by the maximum jump the PLL will have to accomplish when operating in its allocated frequency band. The step-size for GSM-900 is 45 MHz and for GSM-1800 is 95 MHz.The required frequency tolerances are 90 Hz and 180 Hz,respectively.The PLL must complete the required frequency step in less than 1.5 time slots,where each time slot is 577 µs. All trademarks and registered trademarks are the property of their respective holders. Figure 2.Dual PLL used to mix down from GSM RF to baseband. Figure 1.Block diagram of a PLL. 2 Analog Dialogue 36-03 (2002) Q .I ’ve selected my synthesizer based on the output frequency required. What about choosing the other elements in the PLL?
Q. A.Frequency Reference :A good,high quality,low-phase-noise reference is crucial to a stable low-phase-noise RF output.A square wave or clipped sine wave available from a TCXO crystal offers excellent performance,because the sharper clocking edge results in less phase jitter at the R-counter output.The ADF4206 family features on-board oscillator circuitry allowing low cost AT-cut crystals to be used as the reference.While predictable AT crystals cost one third as much as TCXOs,their temperature stability is poor unless a compensation scheme with a varactor is implemented. VCO :The VCO will convert the applied tuning voltage to an output frequency.The sensitivity can var y drastically over the full frequency range of the VCO.This may make the loop unstable (see loop filter ).In general,the lower the tuning sensitivity (Kv)of the VCO,the better the VCO phase noise will be.The synthesizer phase noise will dominate at smaller offsets from the carrier.Farther away from the carrier,the high-pass-filtered noise of the VCO will begin to dominate. The GSM speci f i cati on f or out-of -band phase noi se i s –130 dBc/Hz at a 1-MHz offset. Loop Filter :There are many different types of loop filter.The most common is the third-order integrator shown in Figure 3. In general,the loop filter bandwidth should be 1/10 of the PFD frequency (channel spacing).Increasing the loop bandwidth will reduce the lock time,but the filter bandwidth should never be more than PFD/5,to avoid significantly increasing the risk of instability. Figure 3.A third-order loop filter.The R2C3 pole provides extra attenuation for spurious products. A loop filter ’s bandwidth can be doubled by doubling either the PFD frequency or the charge-pump current.If the actual Kv of the VCO is significantly higher than the nominal Kv used to design the loop filter,the loop bandwidth will be significantly wider than expected.The variation of loop bandwidth with Kv presents a major design challenge in wideband PLL designs, where the Kv can vary by more than 300%.Increasing or decreasing the programmable charge-pump current is the easiest way to compensate for changes in the loop bandwidth caused by the variation in Kv.

Q.How do I optimize PLL design for phase noise?
Q. A.Use low N-value :Since phase noise is multiplied up from the PFD (reference frequency)at a rate of 20 log N ,reducing N by a factor of 2 will improve system phase noise by 3 dB (i.e., doubling the PFD frequency reduces phase noise by 10 log2). Therefore the highest feasible PFD frequency should always be used. Choose a higher frequency synthesizer than is required :Operating under the same conditions at 900 MHz,the ADF4106 will give 6-dB better phase noise than the ADF4111 (see Table 1). Use the lowest Rset resistor specified for operation :Reducing the Rset increases the charge-pump current,which reduces phase noise. Table 1.The integrated phase jitter depends heavily on the in-band phase noise of the synthesizer.System parameters: [900-MHz RF,200-kHz PFD,20-kHz loop filter ] Synthesizer Model In-Band Phase Noise (dB) Integration Range (Hz) Integrated Phase Error Degrees rms ADF4111 –86 100 to 1 M 0.86 ADF4112 –89 100 to 1 M 0.62 ADF4113 –91 100 to 1 M 0.56 ADF4106 –92.5 100 to 1 M 0.45

Q.Why is phase noise important?
Q. A.Phase noise is probably the most crucial specification in PLL selection.In a transmit chain,the linear power amplifier (PA) is the most difficult block to design.A low-phase-noise LO will give the designer greater margin for non-linearity in the PA by reducing the phase error in the up-conversion of the baseband signal. The system maximum phase error specification for GSM receivers/transmitters (Rx/Tx)is 5 ° rms.As one can see in Table 1,the allowable PA phase-error contribution can be significantly greater when the phase noise contributed by the PLL is reduced. On the receive side,low phase noise is crucial to obtaining good recei ver sel ect i vi t y (t he abi l i t y of t he recei ver t o demodulate signals in the presence of interferers).In the example of Figure 4,on the left the desired low level signal is swamped by a nearby undesired signal mixing with the LO noise (enclosed dashed area).In this case the filters will be unable to block these unwanted interferers.In order to demodulate the desired RF signal,either the transmit side will require higher output power,or the LO phase noise will need to be improved. Figure 4.A large unwanted signal mixing with LO noise swamps the wanted signal.Increased phase noise will reduce the sensitivity of the receiver,since the demodulator will not be able to resolve the signal from the noise.

Q.Why are spur levels important?
Q. A.Most communication standards will have stringent maximum specifications on the level of spurious frequency components (spurs )that the LO can generate.In transmit mode,the spur levels must be limited to ensure that they do not interfere with users in the same or a nearby system.In a receiver ,the LO spurs Analog Dialogue 36-03 (2002)3 can significantly reduce the ability to demodulate the mixed- down signal.Figure 4 shows the effect of reciprocal mixing where the desired signal is swamped with noise due to a large undesired signal mixing with noise on the oscillator.The same effect will occur for spurious noise components. A high l evel of spur s can indirectly affect lock time by forcing the designer to narrow the loop bandwidth —slowing response —in order to provide sufficient attenuation of these unwanted components.The key synthesizer specifications to ensure low reference spurs are low charge-pump leakage and matching of the charge pump currents .

Q.Why is lock time important?
Q. A.Many systems use frequency hopping as a means to protect data security,avoid muti-path fading,and avoid interference.The time spent by the PLL in achieving frequency lock is valuable time that cannot be used for transmitting or receiving data;this reduces the effective data rate achievable.Currently there is no PLL available than can frequency-hop quickly enough to meet the timing requirements of the GSM protocol.In base-station applications,two separate PLL devices are used in parallel to reduce the number of wasted slots.While the first is generating the LO for the transmitter,the second PLL is moving to the next allocated channel.In this case a super-fast (<10-µs)settling PLL would significantly reduce the bill of materials (BOM) and layout complexity. Figure 5.Loop bandwidth has a significant effect on the lock time.The wider the loop bandwidth,the faster the lock time, but also the greater the level of spurious components.Lock time to 1 kHz is 142 µs with a 35-kHz LBW —and 248 µs with a 10-kHz LBW. Loop Bandwidth .The wider the loop bandwidth,the faster the lock time.The trade-off is that a wider loop bandwidth will reduce attenuation of spurious products and increase the integrated phase noise.Increasing the loop bandwidth significantly (>PFD/5)may cause the loop to become unstable and permanently lose lock.A phase margin of 45 degrees produces the optimum settling transient. Avoid tuning voltages nearing ground or Vp .When the tuning voltage is within a volt of the rails of the charge pump supply (Vp),the charge pump begins to operate in a saturation region. Operation in this region will degrade settling time significantly; it may also result in mismatch between jumping-up in frequency and jumping down.Operation in this saturation region can be avoided by using the maximum Vp available or using an active loop filter.Using a VCO with a higher Kv will allow Vtune to remain closer to Vp/2 while still tuning over the required frequency range. Choose plastic capacitors .Some capacitors exhibit a dielectric memory effect,which can impede lock time.For fast phase locking applications ‘plastic-film ’ Panasonic ECHU capacitors are recommended.

Q.Wh a t f a c t o r s d e t e r mi n e t h e ma x i mu m P F D f r e q u e n c y I can use?
Q. A.In order to obtain contiguous output frequencies in steps of the PFD frequency FPFD A and B >2 in the programming registers.

Q.Fractional-N has been around since 1970.What are its advantages to PLL designers?
Q. A.The resolution at the output of an integer-N PLL is limited to steps of the PFD frequency.Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency.It is possible to generate output frequencies with resolutions of 100s of Hz,while maintaining a high PFD frequency.As a result the N-value is significantly less than for integer-N.Since noise at the charge pump is multiplied up to the output at a rate of 20 logN,significant improvements in phase noise are possible.For a GSM900 system,the fractional-N ADF4252 offers phase noise perfor mance of –103 dBc/Hz,compared with –93 dBc/Hz for the ADF4106 integer-N PLL. Al s o of f er i ng a s i gni f i cant advant age i s t he l ock-t i me i mprovement made possi bl e by f racti onal -N.The PFD frequency set to 20 MHz and loop bandwidth of 150 kHz will allow the synthesizer jump 30 MHz in <30 µs.Current base stations require 2 PLL blocks to ensure that LOs can meet the timing requirements for transmissions.With the super-fast lock times of fractional-N,future synthesizers will have lock time specs that allow the 2 “ping-pong ” PLLs to be replaced with a single fractional-N PLL block.

Q.If fractional-N offers all these advantages,why are integer-N PLLs still so popular?
Q. A.Spurious levels!A fractional-N divide by 19.1 consists of the N-divider dividing by nineteen 90%of the time,and by twenty 10%of the time.The average division is correct, but the instantaneous division is incorrect.Because of this, the PFD and charge pump are constantly trying to correct for instantaneous phase errors.The heavy digital activity of the sigma-delta modulator,which provides the averaging function,creates spurious components at the output.The 4 Analog Dialogue 36-03 (2002) digital noise,combined with inaccuracies in matching the hard-working charge pump,results in spurious levels greater than those allowable by most communications standards. Only recently have fractional-N parts,such as the ADF4252, made the necessary improvements in spurious performance to allow designers to consider their use in traditional integer-N markets.


COMMENT Uncategorized

  1. PLL

    A phase-locked loop (PLL, or phase lock loop) is a control system that generates a signal that has a fixed relation to the phase of a “reference” signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase.
    Phase-locked loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors.