phase locked loop design

The phase-lock-loop (PLL) is commonly used in microprocessors to generate a clock at high frequency (Fout=2GHz for example) from an external clock at low frequency (Fref = 100MHz for example). The PLL is also used as a clock recovery circuit to generate a clock signal from a series of bits transmitted in serial without synchronization clock (Figure 12-50). The PLL may also be found in frequency demodulation circuits, to transform a frequency varying waveform into a voltage.

The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter (figure 12-51). The PLL includes a feedback loop which aligns the output clock ClkOut to the input clock ClkIn through a phase locking stabilization process. When locked, the high input frequency fout is exactly N. ƒin. A variation of the input frequency ƒin is transformed by the phase detector into a pulse signal, which is converted into variation of the analog signal Vc. This signal changes the VCO frequency, which is divided by the counter and changes clkDiv according to ƒin.

Phase Detector

The most simple phase detector is the XOR gate. The XOR gate output produces a regular square oscillation PD_Out when the input clkIn and the signal divIn have one quarter of period shift (or 90° or π/2). For other angles, the output is no more regular. In figure 12-52, two clocks with slightly different periods are used in Dsch2 to illustrate the phase detection.

At initialization, the average value of the XOR output VPD is close from 0. When the phase between clkDiv and clkIn is around Π/2, VPD is VDD/2. Then it increases up to VDD. Consequently, VPD and the phase difference are linked by expression 12-10. For example, when ΔΦ=Π/2, VPD is VDD/2.

The gain of the phase detector is the ratio between VPD and ΔΦ. The gain is often written as KPD, with an expression derived from equation 12-10, which is valid for ΔΦ between 0 and π, as drawn in figure 12-53.

When the phase difference is larger than π, the slope sign is negative until 2π. When locked, the phase difference should be close to π/2.


The filter is used to transform the instantaneous phase difference VPD into an analog voltage Vc which is equivalent to the average voltage VPD. The rapid variations of the phase detector output are converted into a slow varying signal Vc which will later control the voltage controlled oscillator. Without filtering, the VCO control would have too rapid changes which would lead to instability. The filter may simply be a large capacitor C, charged and discharged through the Ron resistance of the switch. The Ron.C delay creates a low-pass filter. Figure 12-54 shows an XOR gate with the output charged with a large poly/poly2 capacitor and a serial resistance to create the desired analog voltage control Vc.

the filtered version of the XOR gate output VPD is shown. It can be seen that VPD is around VDD/2 when the phase difference is Π/2 or -Π/2. The duty cycle of the phase detector output should be as close as possible to 50%, so that Vc is very close to VDD/2 when the inputs are in phase. If this is not the case, the PLL would have problems locking or would not produce a stable output clock. The XOR gate layout has been modified so that the output voltage Vc is very close to VDD/2 when one input in fixed to ground and the other input is a regular clock.

Voltage Controlled Oscillator for PLL

Important characteristics of the PLL can be listed:

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