Parity checkers are integrated circuits (ICs) used in digital systems to detect errors when streams of bits are sent from a transmitter to a receiver. Parity generators calculate the parity of data packets and add a parity amount to them. Both parity checkers and generators use parity memory, a basic form of error detection which provides an extra bit for every byte stored. Whenever a byte is written to memory, the parity circuit examines the byte and determines whether it contains an even or odd number of ones. If the data byte contains an even number of ones, the extra (parity) bit is set to 1; otherwise, the parity bit is set to 0. When the data is read back from memory, the parity circuit examines all of the bits and determines if there are an odd or even number of ones. An even number of ones indicates that there is an error in one of the bits because a parity circuit, when storing a byte, always sets an error-free parity bit to indicate an odd number of ones. When a parity error is detected, the parity circuit generates a non-maskable interrupt (NPI) that halts the processor, ensuring that the error does not corrupt other data.