Layout of operational amplifier
The example shows here is the layout and verification of the most important building block in analog integrated circuit operational amplifier.
the steps are follows ( Only layout discussion not circuit design )
A. Enter Schematic
B. Pre-layout Simulation Using Spectre
C. Custom Layout Using Virtuoso
D. Extraction and LVS
E. Post-Layout Simulation Using Spectre
Figure 1. Complete OTA Schematic
Note that ‘L’ has been chosen much larger than the minimum. This is done to
improve matching and increase gain. Also note that all devices have been specified
as having two gate fingers. To set this parameter change the ‘Multiplier’ field
in the device properties to two.
B. Pre-Layout Simulation:
Figure 2. Pre-Layout Simulation
C1. Layout of 1-Gate Finger
layout of the N2, N3 current mirror. Here is the
layout of one transistor finger. It measures 10.8um by 2.1um.
Figure 3. One NMOS Transistor Finger
Note: We don’t have to worry about substrate contacts yet.
C2. Combine 4-Gate Fingers for N2, N3 current mirror
Next array 4 gate fingers to create the shared source/drain
structure. This will allow us to implement an ‘ABBA’ common centroid.
Figure 4. Layout of all gate fingers for N2,N3 Mirror.
C3. Add drain and gate routing for N2, N3 current mirror.
Here is N2,N3 with the drain and gate routing. Note the shared
source/drain structure. The sources are floating right now. Once
the body ties are included the sources will be routed to the body ties.
Figure 5. Layout of N2,N3 with routing.
Figure 6. Layout of N2,N3 with routing and annotation.
C4. Add N4, N5 to complete NMOS current mirrors.
added N4, N5 using the same ‘ABBA’ structure. They are
placed outside of the N4,N5 mirror, similar to the schematic. Note
that since all there structures are very similar,
Figure 7. Layout of N2,N3,N4,N5.
Figure 8. Layout of N2,N3,N4,N5 with annotation.
C5. Layout of NMOS Differential Pair
The NMOS current mirrors are complete for now, next
is the differential pair N0, N1. Again I used the ‘ABBA’
Figure 9. Layout of N0, N1.
Figure 10. Layout of N0,N1 with Annotation.
C6. Layout PMOS Current Mirrors
Now we can layout the P transistors. I used the same structure
for these and put the P0, P3 mirror on the left and the P1,P2
mirror on the right. Again, the placement of the mirrors is similar
Figure 11. Layout of P0, P1, P2, P3.
Figure 12. Layout of P0, P1, P2, P3 with Annotation.
C7. Substrate Plugging
Now that all of the individual cells are complete, it is time to
add substrate plugs. It is good to add a complete ring around
each cell. It is not absolutely necessary to add the ring
all the way around the differential pair, but it should help
Figure 13. Layout of cells showing substrate plugs.
C8. Final Routing
All that is left is final routing. I routed all sources to the
well ties using metal 2. All routing between cells is done with
metal 2, so that the well tie can be crossed.
D. Extraction and LVS
Next extract the layout and run LVS to make sure that everything is
Figure 15. OTA Extraction
E. Post Layout Simulation
Figure 16. Post Layout Simulation