on chip decoupling capacitors

on chip decoupling capacitors (decaps) are used to reduce the dynamic supply noise from simultaneous switching events.Unfortunately, unless enough decap cells are placed in close proximity to the dynamic “hot spots” in a design, their effectiveness is greatly diminished.

Typically, an ad-hoc methodology is used to simply fill empty spaces with decaps after P&R and clock tree routing. Without an accurate and systematic means to analyze their effectiveness, decap cells can be put in places where they have little or no effect, contributing only to additional leakage power which could become critical, especially
in today’s low-power designs.

As we are moving to lower technology nodes like 45 nm , 32 nm , it would be a good idea if one can distribute decap uniformly just after early placement stage .Although this maynot address the local hotspots & this can reduce the drop globally , especially as at later stage in design flow one may not have the space to place decaps in certain regions.Would be great if anyone can share their thoughts on early stage decap placement methodology .

An early stage decap placement is a good idea indeed. However we need to see the cost of adding decaps. Usually the power drop is significant when the logic is switching at high frequency and when the power source is away from hotspot.
High frequency logic also means that it will be timing critical too. so if we plan to introduce decap early in cycle that means we are eating up silicon space which may be required to close timing efficiently.
Most of the designers do not like this idea and prefer to take care of power drop in other fashions. One of which could be filling the empty spaces with decaps then performing power analysis and then on case by case basis resolving hot spot issue.
Incase timing is really very critical then it is better to enhance the power grid to such an extent that the static IR drop is minimal, say less than 3% VDD-VSS combined. in that case dynamic IR drop may not be very bad even if logic switching freq. is high. Flipchip device is also another means to take care of power droops.
An intermediate technique could be to add decaps colomn or rows in the floorplanning stage itself so that there is a grid of capacitors alongside grid of power network rails. I have not done any analysis with such a structure but I believe this will overall boost the performance of power network.

The Dynamic drop is governed by the simultaneous switching. Effective decap insertion can be when this simutaneous switching is determined after the placement. So, just like the router does search and repair loops after routing to fix DRCs, similar mechanism need to be adopted at placer level where after placement the tool does a hotspot estimation and a repair loop to effective insert decaps.

There may be a second purpose to “on-chip” de-coupling in wireless devices, With RF links moving into the 5-10 GHZ range, the conventional, off-chip networks of 0.1uf and 0.01uf ceramic capacitors do not provide enough RF by-pass under some circumstances (Especially around low level PLL/DLL circuits) This is because the self resonant frequency of the ceramic capacitors is often below 1GHZ.

Decaps in lower technologies are not much effective due to gate leakage and therefore avoided. There are some other techniques to reduce SSN such as using distributed power driver, multi-point sensing and embedded power/ground pads.


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