Methodology for Simultaneous Noise and Impedance Matching in LNA
This paper presents a step-by-step methodology for simultaneous noise and input impedance matching in CMOS and SiGe W-band LNAs. This technique yields either increased gain or reduced power dissipation. Additionally, techniques to determine the optimum layout for MOSFETs in mm-wave LNAs are discussed. Measurement results in 90nm CMOS show a 1-stage 1.8V, 78GHz LNA with 3.8dB gain and 16mW power dissipation, and a 1.8V, 2-stage 94GHz LNA with 4.8dB gain, and 30mW power dissipation. In all cases S11 and S22 are lower than -10 dB. The low-noise amplifier is a critical building block in almost every radio system. Several SiGe V-band (50- 75GHz) and W-band (75-110 GHz) LNAs have been reported. The development of CMOS mm-wave LNAs is strictly below 60GHz and has lagged SiGe development . Here, the first W-band 90nm CMOS LNAs, using improvements to an existing gigahertz-range noise and impedance matching technique, are presented. Traditional LNA design employed lossless reactive components to transform the signal source impedance to the optimum noise impedance of a transistor biased at NFmin current density . Unfortunately this methodology compromises the input impedance matching. In integrated circuit LNAs, the designer can control the optimum noise impedance and bias current of the input transistor by adjusting its emitter length (or gate width). Thus, it is possible to obtain simultaneous noise and impedance match at the input of a SiGe or CMOS integrated circuit LNA. The methodology in however, has two important limitations that arise in mm-wave LNAs.