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low power vlsi techniques


Transistor sizing
Progressive transistor sizing
fet closest to the output is smallest of series fets
Transistor ordering
put latest arriving signal closest to the output
Logic structure reordering
replace large fan-in gates with smaller fan-in gate network
Logical effort
Buffer (inverter) insertion
separate large fan-in from large CL with buffers
uses buffers so there are no more than four TGs in series





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