Low Power DSP for Wireless Communications

This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture—Signal processing On Demand Architecture (SODA)—which is a four-processor, 32-lane SIMD machine that was optimized for WCDMA 2 Mbps and research 802.11a. SODA has several shortcomings including large register file power, wasted cycles for data alignment, etc., and cannot satisfy the higher throughput and lower power requirements of emerging standards. We propose SODA-II, which addresses these problems by deploying the following schemes: operation chaining, pipelined execution of SIMD units, staggered memory access, and multicycling of computation units. Operation chaining involves chaining the primitive instructions, thereby eliminating unnecessary register file accesses and saving power. Pipelined execution of the vector instructions through the SIMD units improves the system throughput. Staggered execution of computation units helps simplify the data alignment networks. It is implemented in conjunction with multicycling so that the computation units are busy most of the time. The proposed architecture is evaluated with an in-house architecture emulator which uses component-level area and power models built with Synopsys and Artisan tools. Our results show that for WCDMA 2 Mbps, the proposed architecture uses two processors and consumes only 120 mW while SODA uses four processors and consumes 210 mW when implemented in 0.13- m technology and clocked at 300 MHz.

RECENT years have seen an emergence of a large number
of protocols that cater to different types of wireless communication networks. In these protocols, baseband processing is
one of the most computationally demanding parts and is usually
realized with ASICs for power efficiency. But ASIC-based hardwired solutions are costly because of the large number of existing and upcoming wireless standards. Software-defined radio
(SDR) provides a cost-effective and flexible solution for implementing multiple wireless protocols in software. In this paper,
we present a programmable, high-throughput, low-power processor for baseband processing. Designing such a processor is

challenging, because programmability is usually achieved at the
cost of energy efficiency.

this paper we present a programmable baseband processor,
SODA-II, that takes advantage of the inherent parallelism in
novel ways to further increase energy efficiency for current and
emerging standards.
Previously we developed a low-power programmable multiprocessor architecture, Signal processing On Demand Architecture (SODA) [7], for supporting wireless baseband processing
protocols such as W-CDMA 2 Mbps and research 802.11a
[15]. Each processor consists of a 16-bit and 32-lane SIMD
datapath to handle the vector computations, a scalar datapath,
scratch pad memories, address generation unit, and DMA support. The main drawbacks of SODA are that it spends a signifi-
cant amount of time on noncomputational operations such as realigning data through a shuffle network and performing a large
number of register file accesses. This is quite typical of wide
SIMD architectures, and similar observations have been made

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