Layout methodologies that reduce latch up effect
• Avoid routing power supply lines (especially to substrate or tub contacts) in
resistive materials such as diffusion or polysilicon. Keep the power nodes
• Place substrate and tub contacts between transistors of different types. In
addition minimize the distance between substrate contacts and transistors
within a well and vice versa. For example, if PMOS transistors are within an
N-WELL then place the P-type substrate contacts as close as is allowed to
the PMOS transistors. Apply the same logic to the N-type tub contact spacing
to NMOS transistors.
• Maximize the number of substrate and tub contacts.
• Minimize the spacing between substrate and tub contacts.
• Ensure an even coverage of substrate and tub contacts over the entire area.
• Use continuous strips or bands of substrate and tub contacts. This technique
is formally known as guard banding, especially when the bands completely
surround transistor areas.
• Group transistors of the same type together to avoid the overhead of having
to protect against latch-up in many different areas.