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Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal and Analog Integrated Circuits


Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.

As semiconductor technology continues to shrink, process variation problems will become inevitable. It is anticipated that the problem of uncontrollable process variation will become more serious. As a result, yield loss caused by process variation is becoming an important design issue. Yield loss is typically divided into the following two categories: parametric yield and defect-related yield. These losses are caused by process variation and defects, respectively. To analyze process variation in early design stages, process variation information must be input to a circuit simulator, where Monte Carlo analysis is commonly employed. More specifically, a circuit simulator applies statistical variances to device parameters and draws random values for simulations. However, statistical design and analysis processes are time consuming. The key performance of many analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold, is directly related to accurate capacitance ratios [1]. Capacitance ratio mismatch problem can be alleviated by using parallel unit capacitances [2], and the precision of the unit capacitance array can be further improved by common centroid structures [2]–[4]. These structures significantly reduce the effects of gradients and random errors in fabrication. Perfectly matched devices must satisfy the following four conditions [5]: coincidence, symmetry, dispersion, and compactness. A number of layout rules were developed to guide designers to develop an appropriate layout that meets these conditions [2]–[4]. However, the layout shape must be a rectangle to meet these four conditions. Moreover, which condition achieves better matching is generally difficult to determine without performing the time-consuming yield evaluation process. At the time of this writing, no simple rules are available in the literature to measure the degree to which the common centroid conditions are met. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuit design with the switched-capacitor (SC) technique. This paper also develops the relationship between correlation and variation of capacitance ratio. Basically, the dispersion degree of the unit capacitances for both Cs and Ct determines their degree of correlation. The results of this paper will show that the higher dispersion degree results of both Cs and Ct have higher correlation and vice versa. This directly confirms the “dispersion” condition of common centroid [5]. Thus, the correlation coefficient can be used to measure the degree to which the common centroid conditions are met without performing the yield evaluations. In general, the lower variation of capacitance ratio results in higher chip yield. A direct relationship exists between the correlation and yield enhancement, and this relationship can be used to determine whether the selected layout has the sufficient correlation (the degree of dispersion) to meet the given yield requirement. Thus, the effective process provides the degree of design quality improvement using the common centroid structures.

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