image compression in System on Chip -free technical paper
The complexity of modern embedded multimedia systems, which are increasingly based on heterogeneous MultiProcessor System on Chip (MP-SoC), has led to the emergence of system level design. The use of MP-SoC allows the efficiency of multi- processor even using parallelism between tasks and the flexibility of using software applications instead of hardware. System level design for MP-SoC based embedded systems however still involves a substantial number of challenging task. For exam- ple, applications need to be discomposed into paralell specifications so that they can be mapped onto a MP-SoC architecture. Subsequently, applications need to be par- titioned into HW and SW parts since MP-SoC architectures often are heterogeneous (hardware and software) in nature.
To cop with this design complexity, system-level design aims at raising the ab- straction level of the design process, for example, with the use of architectural plat- forms to facilitate re-use of IP components and the notion of high-level modeling and simulation. The latter allows for capturing the behavior of platform compo- nents and their interactions at a high level of abstraction. As such, these high-level models minimize the modeling effort and are optimized for execution speed, and can therefore be applied during the very early design stages. Several Dutch universities work in this System Level Design direction inside the Artemisia project creating the Daedalus framework to address these system-level design challenges.
The main challenges of this MP-SoC design tool are:
1. The partition of the application into concurrent processes.
2. The simulation of this processes in a high level of abstraction.
3. The Multi-Processor platform generation.
4. The mapping of the application processes onto the multiprocessor platform.
5. The fast modification of the application on response to user requirements or bugs.