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high speed interconnection issues


While not a traditional “RF” technology, the interconnection requirements of high-speed digital systems will increasingly drive the performance of wideband transmission line technologies. CPU functionality has increased 1000X about every 12 years, leading some to claim that the bandwidth of CPU connections needs to increase tenfold every four years to keep up with CMOS scaling. Historically most computer busses are as wide as the data and address words and operate synchronously. As higher speeds are required, parallel busses are being replaced by multiple self-clocked serial ports, such as the PCI Express standard. These ports typically use four lines, with two differential conductors for each direction. The initial speeds will be 2.5 Gbps and then increase to 10 Gbps or higher.

But copper conductors fundamentally distort and attenuate fast time-domain signals. It is well known that skin-effect losses increase as the square root of frequency. Pre-emphasis (equalization) is often used in output drivers to compensate for the frequency-dependent transmission line losses due to skin effect and dielectric losses above 1 GHz. However, the larger scaling problem is that the dimensions of a mode-free TEM transmission line must be scaled in the transverse direction inversely with the maximum frequency used, to avoid distortion from multi-mode propagation. So the loss of a scaled mode-free TEM line effectively increases as the 1.5 power of its maximum useable frequency (assuming negligible dielectric losses). At 110 GHz, typical coaxial lines exhibit loss of ~0.4 dB/cm, so the bandwidth of wideband copper interconnects quickly becomes a limiting factor.

Optical interconnects have been proposed as a means for achieving more bandwidth within a rack, since over 1 Tbps has been demonstrated on one fiber for long-haul telecomm systems. However the cost, size, or power consumption of these wavelength-division multiplexed systems are not applicable within a rack, where for example many inexpensive 100 Gbps connections will be required between boards. Directly-modulated sources are difficult above about 10 Gbps, fiber interfacing techniques are expensive and complicate packaging requirements, and monolithic integration of optical and electro-optic functions has yet to be proven.

Within a large digital chip the interconnect problem is similar, if not more challenging [1 (Interconnect chapter)]. The on-chip delay from interconnect wiring scales in the wrong direction and dominates on-chip delays with device gate sizes smaller than about 250 nm. Using more interconnect metal layers with unscaled dimensions improves the delay performance but increases the chip cost from extra processing of more metal layers. On-chip optical interconnects using integrated waveguides have been proposed as a solution for on-chip global wiring, but feasibility of inexpensive Si-compatible integrated sources and detectors has not been shown. To minimize the effects of slow global wiring, repeatered lines and interconnect-centric architectures and design tools will likely be adopted.





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