high speed divider

By comparison, the conventional programmable divider consists of a dual-modulus prescaler (DMP), a program (P) counter and a swallow (S) counter and is depicted in the block diagram shown in Figure 1. A DMP is used to get higher resolution. A DMP allows the prescaling factor to be changed between N and N+1. Prescaler divides 2.4 GHz down to the 75 MHz, which is used for the following loadable counters to minimize the silicon area and power. Here, a program counter acts as coarse tuner and a swallow counter as fine tuner. The counter/divider M is given as:
M = (N+1) S + N (P – S) = NP + S
For proper functioning of the counters, S should be smaller than P and S must also be less than N. The numbers of N, P and S should be chosen carefully according to the maximum limitation of the allowable input frequency of the counters.
The conventional design has the following issues:
Requires two loadable down-counters.
Reduces speed, due to delay introduced in the counter path.
Increases design complexity while designing the loadable flip-flops.
Reduces robustness of the circuit.
Offers high power consumption at ~24 mW.
Increases hardware and silicon area.
Proposed programmable divider
The proposed programmable divider consists of a dual-modulus prescaler (DMP), an up-counter, an equality detector, an analog MUX and PCFR logic. The conceptual diagram is shown in Figure 2.
In Figure 2, Fin = sinusoidal input frequency, Fout = output frequency, CR = coarse register, FR = fine register and PCFR logic = prescaler, coarse, fine selector and reset generation block. Now the formula for the proposed programmable divider is:
M = {( N * CR ) + ( FR * 2 )}
The DMP divides sinusoidal input signal by either N or N+1. That is, DMP will perform divide-by-32; when MC = 0, and divide-by-33; when MC = 1. Thus, the input frequency is divided down to 75.375 MHz, 77.625 MHz from 2.412 GHz, 2.484 GHz respectively for MC = 0. The up-counter block operates with this downed frequency. The up-counter is itself a programmable frequency divider whose function is to increment the counter output on the rising edge of the downed frequency (CLK) and reset the counter output asynchronously when reset = 1.