 # frequency converter design

In many situations for radio frequency emitters and receivers, there is a need for shifting a input waveform into a lower or higher frequency waveform. From an emission point of view, most of the signal processing is done within the range 10-100MHz. However, the emission bandwidth may be significantly higher (900MHz, 1.8GHz for mobile, 2.4, 5GHz for wireless local area network). A direct generation of the desired signal at such a high frequency would consume too much power. A low power frequency translator circuit is preferred. In the case of figure 12-67, the frequency converter shifts the original signal (Say 100MHz) to the desired emission frequency 900MHz.

The operation which translates a high frequency signal into a low frequency signal is called down conversion. In frequency domain, it consists in shifting a high frequency information contained in frequency fin to a lower frequency flow, as illustrated in figure 12-68. The information contained in the original signal fin (Which may include an amplitude, frequency or phase variation) is preserved in the resulting signal fout.

Adding Sinusoidal Waves

Adding sinusoidal waves is very easy. A simple circuit containing 3 resistor produces the addition of two sinusoidal waves, as shown in figure 12-12. The formulation is easily demonstrated using the superposition theorem.

The Fourier transform of the signal s1+s2 reveals two harmonics (Figure 12-71), one at the frequency of signal 1, the other at the frequency of signal 2, as the formulation 12-12 suggested. Clearly, no frequency shift may be obtained using sinusoidal addition.

Multiplying Sinusoidal Waves

At the core of up/down frequency conversion is the multiplication of two sinusoidal waves in the time domain [Lee Chapter 12]. The result of that multiplication is the generation of two new frequencies: one at the sum of frequency, one for the difference.

If we consider a low frequency fin, and a high frequency fOsc and only consider absolute values, the multiplication of these two sinusoidal signals creates two new sinusoidal contributions: one at fOsc -fin, one at fOsc + fin (Figure 12-72). Using an LC resonant circuit, we only keep the desired frequency contribution. In the case of figure 12-72, the L and C values are tuned to highlight the fOsc + fin contribution, which fits with the emission bandwidth. The LC resonator also serves as a filter of undesired harmonics, such as fOsc – fin and fOsc.

Using a MOS for Sinus Multiplication

The process for multiplying signals with CMOS devices is far from being simple. The nMOS and pMOS are non-linear devices. The best example is the long channel nMOS which gives approximately a square law dependence between Vgs-Vt and Ids, as illustrated in figure 12-73. A linear device would give a linear dependence between Ids and Vgs, which is almost the case for short-channel devices. See chapter 3 for more details about device modeling.

The idea is as follows the two sinusoidal inputs fin and fOsc are added on the gate Vgs. The current Ids is a non linear function of Vgs. The static characteristics of the device (W=50µm, L=0.5µm) show a “quadratic” dependence: each Vgs step induces a square increase of Ids. This can be simply written as:

The most important result beyond this approximation is that the input signal and the oscillator signal are effectively multiplied and create the desired harmonics. In other words, passing a sum of sinusoidal waveforms into a non-linear device create several harmonics, from which fin+fOsc and fin-fOsc are the most important. The desired harmonic is underlined in equation 12-17 by rearranging the product of sinus into a sum of sinus. The term Ids0 also contains the original input signal, the oscillator signal and all their respective harmonics too, which lead to a quite complex output. A band-pass filter is mandatory to eliminate undesired harmonics and amplify the desired signal. The circuit is called a single-balanced mixer.

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