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floor planing of chip


Due to increase in number of components on a chip, floorplanning is important step in Very Large Scale Integration physical design to ensure quality of design. Various iterative approaches have been suggested to carryout floorplanning in Electronic Design Automation tools. Iterative approaches can produce good results but they are slower. In this thesis, we have taken bottom-up, recursive approach to floorplanning. We have also suggested efficient exhaustive search procedure for placing two, three or four rectangular blocks in a floorplan. A rectangular block can either be hard or soft and resultant floorplan can either be slicing or non-slicing. Further more exhaustive search procedure can also be extended for five or more rectangular blocks. We have developed two algorithms, which fall in class of constructive approaches rather than class of iterative approaches. These algorithms use exhaustive search procedure, works in bottom-up constructive manner and they are recursive in nature. These algorithms are very fast compared to other search algorithms and also producing promising results. Complexity of these algorithms is O(n). Experiments results with MCNC circuits indicate that area utilization of about 85-99% can be achieved in very less time then iterative algorithms.





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  1. guru

    It is easy to deal with layout when structural detail at lowest abstraction is available, one knows the exact number of transistors in the circuit and the way they are interconnected. When this type of structural information is not available, one can estimate the area to be occupied by various sub blocks and together with a precise or estimated interconnection pattern, try to allocate distinct regions of the integrated circuit to the specific sub blocks. This process is call floorplanning. It is important to note that functionally equivalent sub blocks have different shapes and terminal positions. This is one of the main characteristics of floorplan-based design, one chooses the shape and terminal positions such that they fit best with the original structure and assumes that there is a way to design the module satisfying the chosen shape and terminal position. Above type of blocks are known as flexible or soft blocks. When the block is flexible one could say that the realization needs an area A. Whichever shape the block will have its height h and its width w have to obey the constraint hw ³ A. Other type of blocks are hard blocks, it means that their shape and terminal positions (pins) are fixed. It is also important to note that area required for interconnection wiring (Routing) can either provided by incorporating them in the area estimations for the blocks or in the case of N-layer metal with over the block routing (wiring), channel less block layouts are the norm of design






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