Electromigration in cmos
Electromigration is an electrochemical effect by which metal ions from the interconnect are attracted towards the positive anode,. This flow of positive ions is induced by the electron flow and is somewhat analogous to the flow of sediment in a river. The consequence is that electromigration results in the depletion and accumulation of material with voids on the cathode side of the wire and hillocks at the anode side. Eventually a void will result in failure of the line as the effective width reduces and the current density in the remaining wire increases to a fusing level. Similarly hillocks can result in a short circuit with adjacent metal lines. The photomicrograph shown in Figure 6 is of an electromigration failure at an interlevel metal via on a modern CMOS process, this is an example of a void failure where the wire has failed as an open circuit.
The problem of electromigration is not new and has been an issue with integrated circuit design for many years. However with reducing geometry size, the current levels at which electromigration limits are reached now approach levels that may be found in individual circuit nets rather than in power busses and the other high power wiring where it has traditionally been an issue. In a modern 100nm copper based CMOS technology, the electromigration current limit for a minimum size wire is around 100uA for 100k power on hours at 100C. Analog circuits may be using operating with currents in the 10uA to 1mA range and so are subject to this limit. Moreover since such circuits typically have nets operating at dc, they can be particularly susceptible to this problem.
During the design of analog circuits, the electromigration limits should be considered and for circuit nets where the limit is approached or exceeded, a property can be attached to the wire at the schematic which can be used during layout and verification to ensure appropriate wire widths are implemented. The use of redundancy techniques can also be useful in this situation, for example using a cluster of vias rather than individual vias for intermetal connections and the same with contact areas from wires onto the devices themselves.