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digital system design conference


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, development and applications.

It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, Modeling, High Level Synthesis, Productive Design Technology and Engineering Flows, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Power Consumption, Computational Power Speed and Performance, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues are covered in DSD.

The 13th Euromicro Conference on Digital System Design (DSD) will take place in Lille, France, from September 1st, 2010 to September 3rd, 2010

CPS, Conference Publishing Services, publishes the DSD Proceedings, which are available worldwide through the research Xplore Digital Library. An extended version of the best papers will be published in a special issue of the ISI-indexed Microprocessors and Microsystems: Embedded Hardware Design journal, printed by Elsevier.

IMPORTANT DATES

Submission of papers: March 15th, 2010.
Notification of acceptance: April 26th, 2010
Camera ready papers: May 31st, 2010
SCOPE

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of digital system design from embedded and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, Modeling, High Level Synthesis, Productive Design Technology and Engineering Flows, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Power Consumption, Computational Power Speed and Performance, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues are covered in DSD.

CPS, Conference Publishing Services, publishes the DSD Proceedings, which are available worldwide through the research Xplore Digital Library. An extended version of the best papers will be published in a special issue of the ISI-indexed Microprocessors and Microsystems: Embedded Hardware Design journal, printed by Elsevier.

MAIN TOPICS

T1: (SCS) – System and circuit synthesis: high-level, behavioral, register-transfer, logic and physical circuit synthesis; arithmetic, signal processing and vector processing units; graphics processing units and hardware accelerators; memory design; communication architecture and protocols; specific circuits and processors; multi-objective optimization observing power, performance, communication traffic, interconnect architecture, layout, technology, reliability, robustness, security, testability and other issues; management of parallel computational resources, memory allocation and hierarchy; hardware/software co-design; mapping of applications to architectures; algorithm architecture matching; transaction level modeling and higher-level modeling; virtual system prototyping; design space exploration; synthesis of asynchronous and dataflow driven systems.

T2: (SoC & NoC) – Systems-on-a-chip and networks-on-a-chip: multiprocessor systems –on-a-chip (MPSoC), generic system platforms and platform-based design; CMP, SMP, SMT, DSP and VLIW (multi)processor architecture and enhancements; 3D MPSoCs; software design and programming models for multicore platforms; GPUs; cell-based platforms; NoC architectural issues, quality of service in NoCs; 3D NoCs; power dissipation and energy issues in SoCs and NoCs; IP design, standardization and reuse; virtual components; system on a system; compiler assisted MPSoC; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded systems.

T3: (RC) – Programmable/re-configurable architectures/adaptable architectures: programmable/re-configurable/adaptable architectures: design methodologies and tools for reconfigurable computing, run-time, partial and dynamic reconfigurability; fine-grained, mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs; systems on re-configurable chip; system FPGAs and structured ASICs and co-processors; processing arrays; programmable fabrics; novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.); adaptive computing devices, systems and software; optimization of FPGA-based cores; novel design algorithms for FPGA features; CAD for placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification; CAD for modeling, analysis and optimization of timing and power; high-level models and tools for FPGAs; rapid prototyping systems and platforms.

T4: (SMVT) – System, hardware and embedded-software specification, modeling, verification and test: design and verification languages; functional, structural and parametric specification and modeling; simulation, emulation, prototyping, and testing at the system, register-transfer, logic and physical levels; co-simulation and co-verification.

T5: (APP) – Applications of (embedded) digital systems with emphasis on design challenges posed by demanding and new applications in fields such as: (wireless) communication and networking; measurement and control; health-care and medicine; military, space, avionics and automotive systems; surveillance and security; networked and electronic media; multimedia design; image and video processing; real time signal processing hardware; digital video technology; consumer electronics; ambient intelligence; wireless sensor networks; ubiquitous, wearable and implanted systems; automotive; environmental; transportation and traffic control.

T6: (ET) – Important issues introduced by emerging technologies (e.g. nanometer CMOS and beyond CMOS technologies, 3D integration, optical, etc) for the circuit and system design, and design methods and EDA tools for solving these issues.

SPECIAL SESSIONS

DSD 2010 will include special sessions focused on hot topics and emerging fields of interest to the digital systems design research community. Proposals for special sessions must include a title, contact information for the session chair(s), and a list of authors who have been or will be contacted to present papers if the session is accepted. Proposals for special sessions should be submitted to the Program Chair (seblopez@iuma.ulpgc.es) before January 14, 2010.

SUBMISSION GUIDELINES

Regular Papers:

Prospective authors are encouraged to submit their manuscripts for review electronically trough the following web page (http://www.conftool.net/dsd2010/) or by sending the paper to the Program Chair via email (seblopez@iuma.ulpgc.es, only if an unexpected web access problem is encountered) before the deadline for submission.
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the required research format: single-spaced, double column, A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors’ names should appear in the submitted manuscript, references included.

Case Studies and Application Papers:

Submissions can be made which report on state-of-the-art digital systems, digital designs, architectures, design methods and/or tools, and (embedded) applications. Papers discussing lessons learned from practical experience, demanding or new applications, and experimental research are particularly encouraged. Manuscripts may be submitted in the same way as regular papers.
CONFERENCE COMMITTEES

DSD STEERING COMMITTEE:

Lech Józwiak, Eindhoven U. of Tech. (NL) (Chairman)
Krzysztof Kuchcinski, Lund U. (SE)
Antonio Nunez, IUMA/U. of Las Palmas GC (ES)
DSD10 GENERAL CHAIRS:

Henry Basson, U. of Lille North of France (ULNF), Littoral (FR)
Smail Niar, U. of Lille North of France (ULNF), Valenciennes (FR)
DSD10 PROGRAM COMMITTEE CHAIR:

Program Chairman: Sebastian Lopez, IUMA/U. of Las Palmas GC (ES)
Deputy Program Chairman: Paris Kitsos, Hellenic Open Univ. (GR)
DSD10 PROGRAM COMMITTEE:

A. Akkas, Koc U., (TK)
A. Lastovetsky, University College Dublin, (IR)
A. Nunez, IUMA/U. of Las Palmas G.C., (ES)
A. Orailoglu, U. of California, San Diego, (US)
A. Pawlak, ITE & SUT, (PL)
A. Postula, U. of Queensland, (AU)
A. Shrivastava, Arizona State U., (US)
B. de Sutter, U. of Ghent, (BE)
B. Juurlink, TU Delft, (NL)
C. Bouganis, Imperial College, (UK)
C. Cornelius, U. of Rostock, (DE)
C. Wolinski, IRISA, Rennes, (FR)
D. Houzet, Grenoble Institute of Technology, (FR)
D. Noguet, Minatec CEA-LETI, (FR)
D. Quaglia, U. of Verona, (IT)
E. Martins, U. of Aveiro, (PT)
F. Leporati, U. of Pavia, (IT)
G. Danese, U. Of Pavia, (IT)
H. Basson, U. of Littoral, (FR)
H. Kubatova, CTU Prague, (CZ)
H.T. Vierhaus, Brandenburg U. of Tech., (DE)
J. Rabaey, U. of California, Berkeley, (US)
J. Sahuquillo, Pol. U. of Valencia, (ES)
J. Tiberghien, U. Libre de Bruxelles, (BE)
J.L. Dekeyser, U. of Lille, (FR)
J.S. Matos, U. of Porto, (PT)
K.Kent, U. of New Brunswick, (CA)
K. Kuchcinski, Lund U., (SE)
K. Popovici, Mathworks Inc., (US)
L. Benini, U. of Bologna, (IT)
L. Fanucci, U. of Pisa, (IT)
L. Jozwiak, Eindh. U. of Tech., (NL)
L. Sousa, U. of Lisboa, (PT)
L.-G. Chen, National Taiwan U., (TW)
M. Figueroa, U. of Concepcion, (CL)
M. Perkowski, Portland St. U., (US)
M. Valero, Pol. U. of Catalunya, (ES)
M. Velev, Aries Design Automation, (US)
N. Bergmann, U. of Queensland, (AU)
N. Dutt, U. of Calif., Irvine, (US)
N. Nedjah, State U. of Rio de Janeiro, (BR)
N. Sklavos, Tech. Inst. Patras, (GR)
O. Koufopavlou, U. Patras, (GR)
P. Athanas, Virginia Tech, (US)
P. Carballo, IUMA/U. of Las Palmas GC, (ES)
P. Kitsos, Hellenic Open Univ., (GR)
P. Schumacher, Xilinx Inc., (US)
R. Drechsler, U. of Bremen, (DE)
R. Ubar, Tallinn Tech. U., (EE)
S. Kumar, Jonkoping U., (SE)
S. Lopez, IUMA/U. of Las Palmas G.C., (ES)
S. Niar, U. Valenciennes, (FR)
T. El-Ghazawi, George Washington U., (US)
T. Luba, Warsaw U. of Tech., (PL)
T. Sasao, Kyushu Ins. of Tech., (JP)
V. Muthukumar, U. of Nevada Las Vegas, (US)
W.Luk, Imperial College, (UK)
W. Stechele, Technical U. Munich, (DE)
Z. Kotasek, Brno U. of Tech., (SI)
DSD permanent homepage is at: http://www.ics.ele.tue.nl/~dsd
US mirror: http://www.dsdconf.org/
Euromicro homepage is at:http://www.euromicro.org/

http://www.dsdconf.org/





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