# differential amplifier design project report

The goal is to design a differential input stage with the specifications mentioned in Table 2. The

parameters regarding the MOS transistors shall be given only after signing the Non Disclosure

Agreement. The students need to calculate the parameters such as the dimensions of the MOS

transistors to fulfill the required specs.

Please note that the designed circuit should be as simple as possible, just to meet the specifica-tions

mentioned in Table 2, for relieving the complexity on the design part since the motive here

is to get familiarity with the design tools. Students are however left free to explore new things but

keep in mind that everything should be wrapped up in the end of the exercise, so take so much

extra burden what you can manage.

IMPORTANT: The input stage designed here will most likely be used in Analog CMOS 2 De-sign

Project. The Project in Analog CMOS 2 carries 35% weight in the final grade.

**Specifications:**

Specified Value / Range Variable Description

Minimum Typical Maximum

Obtained

/Used *

Vdd High Supply Voltage 2.7V 3.3 V

Vss Low Supply Voltage Gnd

CL Load Capacitance 2 pF

Av DC Gain 80

? t Unit Gain Frequency 20 MHz

Ibias Bias Current 10 µA

Ivdd Current Consumption 1mA

PM Phase Margin 80 °

VCM Common Mode Voltage range 1.3V

SR Slew Rate 15V/µs

Table 2: Specifications for the Design Exercise. * Last column to be filled with obtained results

by the group.

Remarks on the Specifications:

Vdd: Choose either of the values, 2.7V, or 3V or, 3.3V for your design. You need not vary or

sweep this in your simulations.

CL: 2pF load is to be simulated. However, you may add additional load capacitance if you need

more compensation (to improve the Phase Margin) for your circuit. Just take care that you in-crease

the bias current to maintain the Slew Rate.

Av: The DC gain should not be less that 80 (38dB) over entire Common-Mode Voltage range.

? t: The Unity Gain Frequency should be at least 20MHz.

Ibias: This does not mean that the input stage should be biased with 10uA. It means that a 10uA

stable bias current source will be provided. Each group will have to decide suitable scaling factor

for the current mirror as per their circuit requirement to bias the input stage. Fig.1 clarifies the

difference between Ibias and Ivdd.

Ivdd: Limits the maximum bias current for the circuit. The biasing current (or the total current

consumption) of the circuit should be kept below 1mA.

Phase Margin (PM): Should be minimum 80 ° in the entire common mode range.

VCM: Common mode voltage range should be minimum 1.5V. This means that the difference be-tween

the maximum common-mode voltage and the minimum common-mode voltage, for proper

operation of the circuit should be minimum 1.5V. In other words, VCM_Max.- VCM_Min.=1.5V

Slew Rate (SR): Is given for a given capacitive load. It specifies the maximum rate of change of

the output voltage. Remember to verify the slew-rate performance each time you increase the

output capacitance.

Here is a suggestion for the design flow:

1. Calculations:

a) Refer the specifications for the parameters you need to achieve and the parameters

that are given to you, for example: DC gain, Unity Gain Frequency, available bias

current, load capacitance, etc.

b) Refer the MOS model summary document and process parameters document to

collect the device parameters, such as: Threshold voltage,µ , Cox, etc.

a) and b) constitute the set of ‘knowns’ for your calculations.

c) Collect the set of ‘unknowns’ needed to achieve the ‘knowns’ in a). Use the

‘knowns’ in a) and b) with suitable equations to calculate the ‘unknowns’. Exam-ple

of ‘unknowns’, for instance is: the transconductance of the input transistors,

the output impedance, the biasing current required, device dimensions etc.

2. An example:

i. Start with the slew-rate specification. Calculate the biasing current from this specification.

ii. Since the biasing current is now known, calculate the size of the biasing transistor – tail cur-rent

mirror (suitable mirroring ratio).

iii. Calculate the transconductance of the input transistors to achieve the required Unity Gain

Frequency with provided load capacitance.

iv. Calculate the required output impedance of the active-load current mirror to achieve the re-quired

DC gain. Calculate the sizes of the load transistors.

Usually one has to iterate a few times in steps i. through iv. along with the simulations to achieve

the required specifications.

This document is provided just as a reference or guidance. Students are not urged not to feel

bound to adopt the flow outlined above for this exercise.

**Report structure**

1. Title Page: With topic, course, group number, name of each candidate in the group.

2. Foreword: Providing the objective of the work and the outline of your report.

3. Contents: Listing individual sections in the report with page numbers.

4. Layout plots: with clearly marked device and port names. Explain the port names. Attach

the final schematic with clearly mentioned device dimensions.

5. Table with final circuit specific parameters – i.e., Data sheet of your design (Gain, UGF,

PM, Common-mode range, etc.) vs. the given specifications – Use Table 2.

6. Mention clearly if design changes were made after submission of the Mid-Term Report. If

yes, then enlist them, explaining the reason(s) to do so.

7. Simulations: Final plots for all the parameters after parasitics extraction – discuss them

individually as in Part I (6). Compare them both with suitable explanation.

8. Conclusion: What did you do? What was achieved? And a summary of your results.

9. Feedback: What did you learn? How was it? Your comments.

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