DFT Interview Question
wht is the diffrence between verification and dft?
difference between defect, fault and failure?
wht is observability and controlability?
wht is scan?
how can we perform scan operation?
wht is serial and parallel loading?
wht is the difference between sequential and combinational atpg?
wht is atpg?
wht is drc violation?
wht is fault model?
how many fault models are there?
wht is scan stiching?
different command option….
wht is bist?
wht is bisa?
wht is bscan?
How is logic transition fault is different from memory transition fault.
What are RAM sequential patterns?
Diff b/w Named Capture Precedures and Clock Procedures
What are the typical scan clock frequencies?
How much is your design count? Complexity?
What is possible cause of simulation mismatches when you simulae the generated ATPG patterns? what is right way to debug them?
how do you solve coverage issues?
what is normal mode and at-speed mode?
what is mbist?
what is dft coverage? how to get high dft coverage?
normal flow for dft ?
Whats the difference between structural and functional vectors?
What the major problem faced in dft with tri-state buffers and how is it resolved.
Which is advantageous, launch at shift or capture launch.
How to achieve high fault coverage. How to increase it.
latch – how is it used in dft for sync two clock domains.
Does the dft vectors test the functionality of the design also?
What does test procedure files have?