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Design for Test in VLSI


Design for Test in VLSI products can reduce cycle time in the following ways:
1. Help generate test patterns before tape-out such that silicon debug and diagnosis can be done faster.
2. Active participation of DFT in RTL coding and verification in writing the RTL to maximize the test coverage is critical. DFT engineers can work with RTL teams in reducing number of RTL cycles and hence the number of physical design cycles.
3. DFT Engineers can and should spend time on reducing test-time. Test-time is part of the product cycle time and it affects a lot of parameters, including and not limited to first silicon debug that keeps the next tape-out waiting, tester cost and fib testing. Tester time is of great importance in high volume products that require zero defects.

In addition to facilitating rapid/productive first-silicon debug post-tapeout, there can be design cycle advantages when DFT features are designed to be re-usable as in-system configuration/debug. For example, if JTAG standards-based TAP hardware is used to access internal registers in a chip for debug/configuration, if scan chains are designed to be accessible for in-system debug through the TAP, or if MBIST structures can be re-usable for in-system memory state debug. The re-use of the DFT structures saves die area, but also can reduce overall design cycle vs. designing/verifying DFT-independent custom configuration/debug features. (This was already alluded in the prior posts, but it seems to me that DFT is typically primarily used for systematic screening/diagnosis of manufacturing defects, but DFT is not necessarily re-usable for in-system debug of functional-mode behavior, unless it is specifically implemented that way.)

In digital design, a properly automated synthesis methodology should mean that digital DFT has almost no negative impact upon the amount of time taken to reach a properly testable impact, which of course means that manufacturing defects can be filtered out as causes of problems in first silicon, so that designers time is spent fixing design problems rather than manufacturing issues.

Digital DfT (ala scan & Mem Bist), one simple answer is that the silicon debug and diagnosis capabilities available at time of 1st Silicon alone can dramatically reduce cycle time to the next design rev and tape-out. Additionally, requiring design teams to generate/simulate atpg patterns prior to tape-out can identify power starvation, IR drop issues, etc. which may not be identified until later in the product life-cycle.





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