design challenges in analog base band circuits for wireless system

The market for mobile telecommunications products has grown rapidly during the last decade. Cellular phones have become mass-produced products in a market in which price is an important factor affecting the success of the product. Price, size, talk, and stand-by times are the most important technical valuation criteria of a mobile phone. Although the analog receiver front-end does not limit the size of a mobile phone, the implementation of the receiver affects the size, battery life, cost, and manufacturability of the product. A lower cost and size can be achieved by increasing the integration level. There is a trend toward single-chip transceivers, in which all active circuitry is integrated into a single chip. Despite the recent rapid progress in the area, some off-chip passive components will remain a necessity in the near future, like antenna and RF pre-select filter.

Second-generation cellular systems have utilized quite narrow signal bandwidths, while RF and IF circuits have dominated the power consumption of the analog part of the receiver. In thirdgeneration systems, like UTRA/FDD WCDMA, the signal bandwidth at baseband is approximately 2MHz. This is much higher than in the second-generation systems. For example, in GSM, the bandwidth is over an order of magnitude narrower. It is evident that the baseband signal processing in a radio receiver will consume more power in the third-generation systems. The significance of optimizing the analog and digital baseband signal processing of a mobile phone will therefore increase in the future.

The choice of receiver architecture affects receiver performance, including sensitivity, selectivity, and power consumption. The superheterodyne architecture has been the dominating radio architecture because it offers the highest sensitivity and selectivity. The good performance is achieved by utilizing off-chip, passive RF image-reject and IF channel-select filters having high dynamic range and selectivity. At the moment, filters having comparable performance cannot be integrated. These off-chip filters are bulky and expensive. Other receiver architectures that offer higher integration levels have recently been researched extensively. Direct/conversion architecture is a promising candidate. In this architecture, the channel-select filtering can be performed on-chip and there is no need to use an image-reject filter before downconversion. It offers the highest integration level available. However, the fundamental problems of the architecture prevented its use in mobile phones until the early 90’s. Because of these problems, some building blocks, especially down-conversion mixers and analog baseband circuit, have stringent specifications that are difficult to meet.

The second- and third-generation cellular systems will co-exist for some time after the new systems have been launched. In the beginning, the new systems will cover urban areas, while rural areas will be covered at a lower pace. The same handset should be able to operate in both the second- and third-generation systems. The different systems can also be used for different purposes. The need for multi-mode radio receivers operating both in the second- and third-generation systems is evident.

Power consumption is of special importance in cellular phones, since power consumption and maximum battery charge determine stand-by and active times. The supply voltage of digital CMOS circuits is decreasing to minimize the power consumption per logic cell. In addition, the shrinking of device dimensions lowers the maximum allowed supply voltage. It is feasible to have a single supply for the whole transceiver, which means that the supply voltage of analog circuits should decrease as well. However, the relation between supply voltage and power consumption is not as straightforward in the analog domain as in the digital. A low supply voltage limits the amount of stacked transistors and leads to a larger number of current branches. On the other hand, the deterioration of the signal handling capability of analog circuitry is not typically allowed. Dynamic range is limited by noise and supply voltage if a sufficient linearity is assumed. In analog circuits, it becomes increasingly difficult to achieve the required performance with low power when supply voltages decrease. Because of the advances in digital CMOS circuit technology and A/D converter (ADC) implementations, the interface between analog and digital signal processing is moving closer to the antenna. Signal processing functions are moved to the digital domain where all nonidealities of the analog domain can be avoided. The ADCs have become the bottleneck in this development. When the analog-to-digital interface is moved closer to the antenna, the performance requirements of the ADCs become more and more stringent, which increases power consumption. In direct-conversion receivers, there will be a continuous-time lowpass filter at baseband. In narrowband systems, this filter can be a simple structure operating as an anti-alias structure for the following ADC or ΔΣ modulator. In low-power, wide-band receivers, probably a more complicated and higher-order filter will be required to effectively attenuate out-of-band signals and make possible a decrease in the required sample rate and dynamic range in the analog-to-digital conversion and clock frequency in the digital back-end. In low-power, wide-band direct-conversion receivers, particular signal processing functions will remain in the analog domain for reasons relating to power consumption.


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