Design and Verification Strategies in cmos process
Design and Verification Strategies
In ensuring that circuit performance is maintained during layout and placement onto a chip, the circuit design and layout process needs to be more tightly connected. The circuit designer has a good understanding of how circuit operation may be affected by parametric shifts but does not always know how layout decisions may affect individual devices. The layout designer knows how individual devices are arranged and has an understanding of how the layout should be arranged for best wiring and signal flow but probably does not have a detailed understanding of circuit operation. Apart from improving the communication between these two operations, the conventional solution to this problem is post layout circuit extraction and resimulation. However this step is not totally rigorous in that the coverage of this simulation tends to be significantly less than that originally performed and so problems may not actually be found. As the system is assembled, this problem is compounded as the complexity increases and the difficulty in identifying individual mismatches increases. The probability of introducing such problems can also increase as circuits are placed adjacent to other structures which may introduce new mismatches.
The following are some design practices that can be used to alleviate these problems:
• Annotating circuit currents and matching requirements more thoroughly on circuit
schematics, not only can these be an aid to layout but they can also be used for verification
• Processing post layout circuit extraction netlists to identify critical devices, the individual
model references can then be examined to check whether they have been modified due to
layout or nearby structures, assuming that this is supported by the extraction tool. This can
allow a quicker and more comprehensive identification of potential problem areas.
• Schematic circuit currents can then be transferred to layout as shape properties. These can
then be used with shapes processing tools to ensure electromigration and self heating limits
on wires and devices are satisfied.
• Using shapes checking tools to identify spacings around critical circuits which, although
compliant with the technology processing ground rules, may cause a problem with device
matching and performance.
• If chip area restrictions permit, ‘guard band’ critical circuits, use any available area and do
not limit layout to the minimum spacings defined by the process ground rules.
• Device models can be ‘biased’ to account for long term shifts in parameters and simulations
rerun with the modified models. In this way, it may be possible to desensitise circuits to such
effects at the design stage.
• Setting voltage limits for gate voltages within simulation, thereby allowing individual devices
to be identified which exceed this limit during simulation testcases. This can allow devices
that are susceptible to gate voltage overstress or NBTI to be more readily identified.