Concepts for Cell and VLSI Chip Design
Every system is made up of building blocks that provide a set of basic operations. The behavior of the system is determined by how the individual units are connected together. If we apply this concept to chip design, then complex systems become tractable, providing the basis for VLSI.
Digital VLSI can be implemented at several levels, depending upon the starting point. The most common divisions are as follows:
Full Custom. Every detail of the integrated circuit layout needs to be completed. At this level, all gates must be designed, drawn, and simulated.
Cell Based. Designs are based on exiting cells stored in a library.
Gate Arrays. Consists of arrays of MOSFETs that can be wired using interconnect lines to implement the desired functions.
Cells and Hierarchy:
Cell is defined as the basic unit in the design. At a logic level, this may be a simple logic function, or a complex boolean operation. The circuit equivalent of a cell is a defined layout pattern with given dimensions, input and output ports, and specified electrical performance.
A system is constructed by interconnecting cells together. At the chip design level, the most important factors
Area and Dimensions. Every cell consumes chip area and has a particular geometrical shape associated with it.
Ports. The location of input and output ports is very important for routing the data path. Also, the power supply and ground are usually needed to provide electrical energy to the cell.
Interconnect Strategy. The cells must be wired together using the interconnect layers.
The cell sometimes is made up entirely of primitives, i.e., that it has only basic geometrical objects such as rectangles and polygons. Some cells are made up from primitives and other basic cells which may also contains cells inside.
The last entry in the Cell Window is Flatten. This command is used to reduce all cells to the level of primitives. The Flatten command is not reversible; once it is applied to the cell, all information concerning instanced cells is lost.
Using Cells in L-Edit:
L-Edit provides very powerful commands for creating, editing, and applying cells in layout drawings. These are accessed from the Cell Window of the Menu Bar. Every drawing in L-Edit is labeled with a file name, with the default name being file0. In addition, a cell is assigned to the drawing on the screen; the default name is cell0. This information is in the upper left corner of the L-Edit screen. It is possible to create cells and store them in the memory. Once cell has been created, it can be replicated as needed in the circuit drawing. Stored cells can be accessed using the Instance Command. When this command is executed, a list of currently available cells is displayed. The cell libraries will be available when the file is opened.
Interconnect wiring usually requires that signals be routed through different layers. It is important to recall that layers can be crossed with only minimal coupling.
POLY can cross METAL1 and METAL2
A POLY contact can be used to create a current flow path to metal
METAL1 and METAL2 can cross
All integrated circuits require power distribution bus lines to supply current to the gates. In CMOS, usually a positive VDD and a ground or VSS must be routed across the die. It is important to use geometrical structure that accommodates the shape of the logic cell