cmosrf modelling

CMOS technology has now reached a state of evolution, in terms of both frequency and noise, where it is becoming a serious contender for radio frequency (RF) applications in the GHz range. Cutoff frequencies of about 50 GHz have been reported for 0.18 µm CMOS technology, and are expected to reach about 100 GHz when the feature size shrinks to 100 nm within a few years. This translates into CMOS circuit operating frequencies well into the GHz range, which covers the frequency range of many of today’s popular wireless products, such as cell phones, GPS (Global Positioning System) and Bluetooth. Of course, the great interest in RF CMOS comes from the obvious advantages of CMOS technology in terms of production cost, high-level integration, and the ability to combine digital, analog and RF circuits on the same chip. This book discusses many of the challenges facing the CMOS RF circuit designer in terms of device modeling and characterization, which are crucial issues in circuit simulation and design.

A Designer’s Guide to CMOS RF Models
In recent years we have begun to see references to “RF” CMOS processes and to “RF” models for those processes. This article will explore what the real meanings of such “RF” designations …
Where it is helpful, we will use these viewpoints to frame the explanations of what is different in RF CMOS and in modeling for it. …
Figure 2: Changes to the modeling of the substrate make the digital CMOS model more reflective of the RF situation. …

For the low-frequency analog and digital designer, this is a relatively ideal substrate – parasitic capacitances returning through the (grounded) substrate see relatively little resistance compared to the capacitive reactance at the frequencies of interest, so simple extraction of parasitic capacitance is very effective in predicting actual performance. But the RF designer would see four negatives: a) the parasitic capacitances are, in effect, maximized by the low resistance of the substrate, and the transmission lines formed by metal interconnects in the oxide over the substrate, as a result, have a relatively low characteristic impedance; b) coils built over the substrate are, in effect, closely coupled to a shorted turn – the substrate itself – thus decreasing both inductance and Q appreciably; c) currents reaching the substrate, whether as currents in capacitive reactances or by induction from coils, travel freely for long distances in the low resistance of the substrate; and d) attempting to improve coil Q by paralleling metal layers helps little, since if the optimal top layer was used first, additional layers are closer yet to the shorted turn in the substrate, and yield little net improvement.