CMOS SuperFlash EEPROM technology

CMOS SuperFlash EEPROM technology and the SST field enhancing tunneling injector split-gate memory cell. The SuperFlash technology and memory cell have a number of important advantages for designing and manufacturing flash EEPROMs, or embedding SuperFlash memory in logic devices, when compared with the thin oxide stacked gate or two transistor approaches. These advantages translate into significant cost and reliability benefits for the user.

The SST SuperFlash technology typically uses a simpler process with fewer masking layers, compared to other flash EEPROM approaches. The fewer masking steps significantly reduces the cost of manufacturing a wafer. Reliability is improved by reducing the latent defect density, i.e., fewer layers are exposed to possible defect causing mechanisms.

The SST split-gate memory cell is comparable in size to the single transistor stacked gate cell (for a given level of technology), yet provides the performance and reliability benefits of the traditional two transistor byte alterable E2PROM cell. By design, the SST split-gate memory cell eliminates the stacked gate issue of “overerase”, by isolating each memory cell from the bit line. “Erase disturb” cannot occur because all bytes are simultaneously erased in the same page and each page is completely isolated from every other page during any high voltage operation.

Field Enhancing Tunneling Injector The field enhancing tunneling injector EEPROM cell is a single transistor split-gate memory cell using poly-topoly Fowler-Nordheim tunneling for erasing and source side channel hot electron injection for programming. Poly-to-poly tunneling is from a field enhancing tunneling injector formed on the floating gate using industry standard oxidation and dry etching techniques. Source side channel hot electron injection is very efficient, thus allowing the use of a small on-chip charge pump from a single low voltage power supply, e.g., 5 or 3 volts. Cells are normally erased prior to programming. The split-gate memory cell size is comparable to traditional stacked gate memory cells using the same process technology. This is possible because:

a) the tunneling injector cell does not need the extra spacing to isolate the higher voltages and currents required for programming the stacked gate array, and

b) floating gate extensions are not needed to achieve the required stacked gate coupling ratios. Additionally, the simplicity of the structure eliminates many of the peripheral logic functions needed to control erasing of the stacked gate device. The tunneling injector cell can be formed using standard CMOS process. Memory arrays may use either random access or sequential access peripheral architectures.

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