CMOS Resistor Layout
considerations for the design of this resistor:
• Choose the width and length of the resistor based on ESD requirements and
• Use more than one contact to connect a signal path
that has the possibility of carrying high currents.
• The width of the metal line should not be minimum and must meet some
kind of electromigration guideline.
• The dashed line between the metal contacts represents the main area of effective
resistance. It not only demonstrates the area available that is effectively
resistive, but it should be a drawn layer that can be used to create devices
for LVS. LVSing these devices ensures that inadvertent changes to the cell
are not made.