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cmos-bsim3-model


The BSIM3 Model
Most CMOS designers have encountered the ubiquitous BSIM3 model is its various revisions, such as BSIM3v2 and others. It was enormously important in the success of CMOS for commercial purposes, because it had a sensible mix of physics-based and empirical parameters, and was readily adapted to new processes. The physics analysis anticipated what would happen as dimensions shrunk, while the empirical components allowed useful approximations of the non-uniform elements of fabricated devices. It is important that the RF designer understand what the implications of this important modeling technique are at the higher frequencies, so we will describe how such a model is created by a typical foundry:

The population of the model’s parameters is typically accomplished by fabricating devices of various channel widths and lengths, which are then curve-traced at DC to yield the parameters that describe transconductance and resistance. Low-frequency capacitance measurements are then made to populate the capacitive parameters. Typically, an optimizer such as the Hspice Optimizer will be used, to massage the model parameters such that the best fit is obtained between actual data and modeled. When the resulting fit is not as close as desired over the entire range of possible device dimensions, the modeler may decide to “bin”, i.e. cause the model to branch on device dimensions to multiple model parameter sets, each optimized for a smaller device size range. This resulting BSIM3 “compact model”, as it is called in the trade, is well suited to rapid execution is simulators, and for use with P-cells (adjustable size parameter physical layout cells) in layout, giving designers great flexibility.

It is important to note what is absent: some device properties are not measured or input to the model–the resistances associated with the gate poly are one important example; nor are any high frequency measurements made. Therefore, the usefulness of the model at high frequencies lies solely in the accuracy as a function of frequency of the equivalent circuit it creates. Fortunately for most purposes, the accuracy is adequate, as the proliferation of commercial CMOS designs bears witness. But let’s examine what the RF designer will find lacking:

If you simulate a BSIM3 device driven from a sweep frequency source and look at the phase angle of the AC current into the gate, relative to the voltage, it stays at 90 degrees. The device input fails to look significantly resistive at high frequencies, as it does in reality due to the series resistance of the polysilicon gate,

How does this manifest itself as a design problem? Minimum Noise Figure for RF devices normally occurs when the source impedance is approximately the geometric mean of the total of series noise sources (such as the 1/Gm-related effective resistances, plus the gate effective series resistance) and the parallel-equivalent input impedance, optimizing the signal to noise voltage ratio. But BSIM3 doesn’t represent the gate resistance as a noise source, or place it in series with the input capacitance, to become the parallel input resistance at a given frequency.

As a result, it is not possible to determine optimum RF noise match, nor accurate simulation of RF noise performance, with the BSIM3 model. And the failure to model the parallel resistive component of input impedance has implications for high-speed digital applications like SERDES: the unmodeled, decreasing the parallel resistive input component with frequency causes both the frequency domain and delay behavior to have significant errors in the gigahertz range.

For many years this situation prevailed because the major CMOS foundries’ modeling groups had neither the familiarity nor the equipment to evaluate their processes at higher frequencies. Eventually, the discrepancy in performance between simulation and actual for RF uses could no longer be ignored, and attempts were made to improve results. But since the BSIM3 model was still very effective for the vast majority of CMOS designers, the first attempts at improvement would be additions outside the BSIM model, rather than significant revision.

The BSIM3-plus-Subcircuit Model
The fundamental problem with the BSIM3 model for RF use was not that it was wrong in itself, but rather that it ignored physical factors that influence high frequency operation. This is illustrated by noting that some foundries have used the very same BSIM3 model inside an RF subcircuit as is used in the digital version of the same process; there is nothing about the way the BSIM3 model is extracted that causes it to be populated differently for a epi vs. uniform substrate of the same resistivity at the device level.

But at higher frequencies, the appreciable resistance in the drain- and source-diode substrate returns, and in the back-gate return, may not be insignificant. Typically, the physical layout used for RF devices will differ, often having heavy gate-head connections (and perhaps even double-headed gates) so as to minimize gate resistance, but also altering the overlap and parasitic capacitances in a dimensionally-dependent way.

So it was easy to gain some improvement by enclosing the BSIM3 model in a subcircuit, Reference 2 and Figure 3, which added R and C passives, and sometimes replaced the BSIM3 source- & drain-diode modeling to reflect the substrate change.

Click to Enlarge Image
Figure 3: Simple enhancements to the BSIM3 model improve its validity.

The device width per finger is typically fixed to one, or a small number, of values, at which subcircuit values have been extracted at common operating points.

But this was to be a way-station on the route to better RF modeling, for there were significant remaining problems:
Simulation speeds slowed, as the subcircuits increased component count, a bigger factor in speed than equivalent increases in compact model complexity.
Subcircuits typically use fixed passives to stand in for what are actually voltage-dependent effects, with the result that distortion and power-efficiency prediction are poorer than desired, and model accuracy degrades at operating points other than the specific operating points at which extraction was done.
The strongly empirical extraction of the subcircuit component values inhibits the use of P-cells for physical layout and easy device size changes in design, since the dimension-dependent subcircuit component values exist outside the compact model and its heavily physics-based approach to adequately predicting behavior in regions between extracted data points. Sizing is typically restricted to the choosing only the number of fingers at fixed width.
Thus, if we take two-port S-parameter data on a grounded-source CMOS device, then look at the same device in a simulator as a BSIM3 model in the same test circuit, the data won’t match well. If we place the device in a subcircuit, the data can be made to match, but only piece-wise, with many component values changing for different operating points. Still, for several years this was the best available approach, and may successful designs resulted.
BSIM4 – A Solution . . . or Not. . .
Fortunately the mainstream moved on as well. The combined effects of ever-shorter channel devices and increasing frequencies in most designs made the shortcomings of BSIM3 more apparent, which caused the BSIM4 model to emerge, Reference 3. What you need to know as an RF designer is that the BSIM4 model can be better, but it is not necessarily so.

This is because the traditional methods of populating the model parameters do not include high frequency correlation, and many of the parameters that improve high frequency accuracy can be either left out, or turned off, leaving the default high-frequency behavior as no improvement over BSIM3! Conversely, if all the capabilities of BSIM4 are used, it can do a good to very good job of matching S-parameter data over all operating conditions at the highest frequencies. So BSIM4 models are preferable to BSIM3+subcircuits models, if the foundry, or service providing the models, has correlated the models at high frequencies.

Similarly, BSIM4 includes back-gate resistance parameters that improve modeling of back-gate effects if the parameters are correctly populated, but few foundries even have suitable test structures developed to take advantage of this capability at present.

While BSIM4 potentially represents a significant improvement in RF-modeling speed and accuracy, it also is not without shortcomings, and two that are presently known are:
It does not include polysilicon gate-depletion effects that alter (increase) the series-equivalent input resistance with decreasing frequency in the 0.1-10GHz range, Reference 4. These effects can be added to BSIM3 or BSIM4 models as an external RC subcircuit, but the resistances and capacitances are strongly non-linear, and we are back to spot-fitting the extracted data at one operating point. Investigators have recently shown that failing to include poly-depletion effects can have a significant impact on SERDES modeling for varying data run-lengths, Reference 5, and equivalent extreme wide-bandwidth RF applications such as UWB PHYs.
The model is not yet fully symmetrical, meaning it doesn’t correctly handle operation in the vicinity of 0 Vds, where source and drain interchange, and thus simulation of such circuits as passive FET mixers and attenuators is not as accurate as the typical drain-elevated regime, Reference 6.
Symmetry is being addressed in BSIM5, currently under development by the BSIM Committee, and while improvements in poly depletion modeling for BSIM5 have not been announced, the on-going research in that area makes it likely for eventual incorporation.





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