CMOS Analog layout guidlines
• In layout of the op-amp, the differential pair matching was very critical. Common centroid technique was adopted and care was also taken so that the source connection was along the common mode line.
• Double rings were employed as protection against latch-up.
• Dummy devices were used at the edges of all matched devices so that variations in poly etch rate wont affect matching.
• The placement of the blocks was such that the inputs and outputs were purely symmetric about the centre (common mode path).
.The compensation capacitors were broken in two equal halves and were connected such that bottom plate of one joins the top plate of the other. This would eliminate any differences in bottom and top pate connection.
• While laying out the whole circuit again care was taken to keep it symmetric about a centre line. The matched capacitor array was placed on top of the op-amp and above that was the switch array. So there was minimum interaction between clock lines and analog portion.
• Capacitor matching was an essential part. Common centroid layout was adopted again. Concept of unit capacitors was used. For the case of non integral ratios the capacitors were divided such that the non unit capacitor was not less than 70% of the unit capacitors (to reduce variability). The more delicate nodes were connected to the top plate as it is less affected by substrate coupling. A shield metal layer was placed on top of the matched capacitor arrays. Dummy capacitors were also used.
• The digital portion was shielded from the analog part by two big capacitors connected between dVdd and gnd. This would suppress transients.