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chip level test free research papers


I. G. Harris, Covalidation of Complex Hardware/Software Systems” in System-on-Chip: Next Generation Electronics, Institution of Electrical Engineers Publishing (Bashir M. Al-Hashimi ed.), 2006.
M. Heath, W. Burleson, I. G. Harris, Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test” , research Transactions on Computers, vol. 54, num. 12, December 2005.
I. G. Harris, Hardware/Software Covalidation” , IEE Proceedings on Computers and Digital Techniques, vol. 152, num. 3, May 2005.
S. Verma, K. Ramineni, and I. G. Harris, An Efficient Control-Oriented Coverage Metric” , research Asian South Pacific Design Automation Conference (ASPDAC), January 2005.
I. G. Harris, Tacking Concurrency and Timing Problems” in Test and Validation of Hardware/Software Systems Starting with System-Level Descriptions, Springer-Verlag Publishing (Matteo Sonza Reorda and Zebo Peng eds.), 2005.
M. Heath, W. Burleson, and I. G. Harris, Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoCs”, research/ACM Design Automation and Test in Europe (DATE) Conference, February 2004.
E. Gaudette, M. Moussa, and I. G. Harris, A Method for the Evaluation of Behavioral Fault Models”, research High-Level Design, Validation, and Test Workshop (HLDVT), November 2003.
D. A. Fernandes and I. G. Harris, Application of Built in Self-Test for Interconnect Testing of FPGAs”,research International Test Conference, September 2003.
I. G. Harris, Fault Models and Test Generation for Hardware-Software Covalidation”, research Design and Test of Computers, volume 20, number 4, July-August 2003.
S. Arekapudi, F. Xin, J. Peng, I. G. Harris, ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems”, Journal for Circuits, Systems and Computers, volume 12, number 3, June 2003.
M. Heath and I. G. Harris A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture”, research Microprocessor Test and Verification Workshop (MTV), May 2003.
Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, Fast Computation of Data Correlation Using BDDs”, research/ACM Design Automation and Test in Europe (DATE) Conference, March 2003.
Q. Zhang and I. G. Harris, Partial BIST Insertion to Eliminate Data Correlation”, research Transactions on Computer-Aided Design, March 2003.
I. G. Harris and R. Tessier, Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures”, research Transactions on Computer-Aided Design, November 2002.
F. Xin and I. G. Harris, Test Generation for Hardware-Software Covalidation Using Non-Linear Programming”, research Workshop on High Level Design Validation and Test (HLDVT), October 2002.
S. Arekapudi, F. Xin, J. Peng, I. G. Harris, ATPG for Timing-Induced Functional Errors on Trigger Events in Hardware-Software Systems” , research European Test Workshop (ETW), May 2002
I. G. Harris, Hardware-Software Covalidation: Fault Models and Test Generation”,research Workshop on High Level Design Validation and Test (HLDVT), November 2001
S. Arekapudi, F. Xin, J. Peng, I. G. Harris, Test Pattern Generation for Timing-Induced Errors in Hardware-Software Systems”, research Workshop on High Level Design Validation and Test (HLDVT), November 2001
I. G. Harris, P. Menon, and R. Tessier, BIST-Based Path Delay Testing in FPGA Arichitectures”, research International Test Conference (ITC), October 2001.
Q. Zhang and I. G. Harris, A Validation Fault Model for Timing-Induced Functional Errors”, research International Test Conference (ITC), October 2001.
W. Burleson, A. Ganz, and I. G. Harris, Educational Innovations in Multimedia Systems”, ASEE Journal of Engineering Education, January 2001.
Q. Zhang and I. G. Harris, A Data Flow Coverage Metric For Validati on of Behavioral HDL Descriptions”, International Conference on Computer-Aided Design (ICCAD), 2000.
I. G. Harris and R. Tessier, Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures”, International Conference on Computer-Aided Design (ICCAD), 2000.
Q. Zhang and I. G. Harris, A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions” , International Test Conference (ITC), October 2000.
I. G. Harris and Russell Tessier, Interconnect Testing of Cluster-based FPGA Architectures”, Design Automation Conference (DAC), 2000.
Q. Zhang and I. G. Harris, Partial BIST Insertion to Eliminate Data Correlation”, International Conference on Computer-Aided Design (ICCAD), 1999.





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