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chip level layout checklist


1. Does the chip meet all packaging requirements? ❑ Yes ❑ No ❑ N/A
2. Are the power supply connections to the pads adequate? ❑ Yes ❑ No ❑ N/A
3. Is the power supply strapping adequate and implemented with ❑ Yes ❑ No ❑ N/A
enough vias?
4. Are the power lines notched anywhere in the top-level routing? ❑ Yes ❑ No ❑ N/A
5. Is the length of all critical path signals optimized? ❑ Yes ❑ No ❑ N/A
6. Have all special signal requirements been satisfied? ❑ Yes ❑ No ❑ N/A
7. Are there adequate spare lines and logic? ❑ Yes ❑ No ❑ N/A
8. Are there probe pads for specified signals? ❑ Yes ❑ No ❑ N/A
9. Is there any sensitive circuitry placed close to the edge of the die? ❑ Yes ❑ No ❑ N/A
10. Are the rules for the chip corner areas satisfied? ❑ Yes ❑ No ❑ N/A
11. Is the interface of the chip to the scribe line properly defined? ❑ Yes ❑ No ❑ N/A
12. Have all ESD and pad latch-up requirements been satisfied? ❑ Yes ❑ No ❑ N/A
13. Have all the necessary chip finishing cells been included? ❑ Yes ❑ No ❑ N/A
14. Is the origin in the center of the die?





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