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Changing the hardware design process with High Level Synthesis – Mentor Graphics seminar


Date: June 08 2010
Changing the hardware design process with High Level Synthesis
RTL design tools have significantly improved over the last 15 years. However, we are using the same design methodology and processes to design a 4G broadband modem or H264 decoder as was employed to design a GSM phone or VGA graphics card.

Using High Level Synthesis (HLS) design groups today are fundamentally changing the way they design hardware as the “traditional” RTL design process is breaking.

This short talk will discuss a 3rd party survey on the motivations for changing the H/W design process to address such issues as RTL design verification, algorithm development schedules, and to cope with the ever increasing design complexity.

The talk will outline the hardware design process with HLS, and demonstrate how hardware IP is designed at a higher level of abstraction.

Finally, the talk will illustrate by example the benefits customer have gained by changing the way they do hardware design by adopting HLS.

Registration Open





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