cadence tutorial


This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.

Design Specifications
Schematic Capture
Symbol Editor
Physical Mask Layout
Design Rule Checking
Layout Versus Schematic
Post-layout Simulation

Technology: 0.8 um twin-well CMOS
Propagation delay of “sum” and “carry_out” signals < 1.2 ns (worst case)
Transition times of “sum” and “carry_out” signals <1.2 ns (worst case)
Circuit area < 1500 um^2
Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW

Unix tutorial – Setting up Unix account
Tutorial 1 – Setting up Cadence tools, MOS IV curves
Tutorial 2 – Schematic Capture, inverter VTC
Tutorial 3 – Simulation with Spectre, transient behavior
Tutorial 4 – Hierarchical Design
Tutorial 5 – Layout and DRC
Tutorial 6 – Extraction and LVS
Tutorial 7 – Synthesis and Place & Route
AHDL Tutorial
Layout Hot Keys

Unix tutorial – Setting up Unix account
Simulation Tutorial – Setting up Cadence tools, Verilog/VHDL simulation
Synthesis Tutorial – RTL compiler
Encounter Tutorial – Backend design, SOC Encounter
Synthesis Tutorials

Design Specifications

The bottom-up design flow for a transistor-level circuit layout always starts with a set of design specifications. The “specs” typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. Note that the limitations spelled out in the initial design specs typically require certain design trade-offs, such as increasing the dimensions of the transistors in order to reduce the delay times.

In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations.

This implies that the designer(s) of individual blocks or modules must communicate clearly and frequently about the spec updates, in order to avoid later inconsistencies.

As an example, the initial design specs of a one-bit binary full adder circuit are listed below:

It can be seen that one can design a number of different adders (with different topologies, different maximum delays, different total silicon areas, etc.), all of which essentially conform to the specs listed above. This indicates that the starting point of a typical bottom-up design process usually leaves the designer a considerable amount of design freedom.

Tutorial links

Cadence Custom Design TutorialsThe following Cadence Top-Down Design Tutorials are used in ECE 686 – Top-Down SOC Design and Implementation:Introduction

Setting Up Your Unix Environment

Starting Cadence

Create Libraries

Schematic entry using Composer

Create Symbols

Simulation with Verilog-XL

Simulation with Hspice

Custom Layout using Virtuoso

Design Rule Check (DRC)

Layout Versus Schematic (LVS) Verification using Diva

Post Layout Simulation

CIF Conversions (CIF IN; CIF OUT)

Sending your IC Chip to MOSIS for Fabrication

Cadence Online Help Manual cadence tutorials

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